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ds971800401 p r e l i m i n a r y 1-1 1 p reliminary p roduct s pecification z80180/z8s180/ 1 z8l180 sl1919 e nhanced z180 m icroprocessor features n code compatible with zilog z80 cpu n extended instructions n two chain-linked dma channels n low power-down modes n on-chip interrupt controllers n three on-chip wait-state generators n on-chip oscillator/generator n expanded mmu addressing (up to 1 mb) n clocked serial i/o port n two 16-bit counter/timers n two enhanced uarts (up to 512 kbps) n clock speeds: 6, 8, 10, 20, 33 mhz n operating range: 5v (3.3v@ 20 mhz) n operating temperature range: 0 c to +70 c n -40 c to +85 c extended temperature range n three packaging styles 68-pin plcc 64-pin dip 80-pin qfp general description the enhanced z80180/z8s180/z8l180 significantly im- proves on the previous z80180 models while still providing full backward compatibility with existing zilog z80 devices. the z80180/z8s180/z8l180 now offers faster execution speeds, power saving modes, and emi noise reduction. this enhanced z180 design also incorporates additional feature enhancements to the ascis, dmas, and i cc standby mode power consumption. with the addition of ?scc-like?baud rate generators (brgs), the two ascis now have the flexibility and capability to transfer data asyn- chronously at rates of up to 512 kbps. in addition, the asci receiver has added a 4-byte first in first out (fifo) which can be used to buffer incoming data to reduce the inci- dence of overrun errors. the dmas have been modified to allow for a ?hain-linking?of the two dma channels when set to take their dma requests from the same peripherals device. this feature allows for non-stop dma operation be- tween the two dma channels, reducing the amount of cpu intervention (figure 1). not only does the z80180/z8s180/z8l180 consume less power during normal operations than the previous model, it has also been designed with three modes intended to fur- ther reduce the power consumption. zilog reduced i cc pow- er consumption during standby mode to a minimum of 10 m a by stopping the external oscillators and internal clock. the sleep mode reduces power by placing the cpu into a ?topped?state, thereby consuming less cur- rent while the on-chip i/o device is still operating. the system stop mode places both the cpu and the on- chip peripherals into a ?topped?mode, thereby reducing power consumption even further. a new clock doubler feature has been implemented in the z80180/z8s180/z8l180 device that allows the program- mer to double the internal clock from that of the external clock. this provides a systems cost savings by allowing the use of lower cost, lower frequency crystals instead of the higher cost, and higher speed oscillators. the enhanced z180 is housed in 80-pin qfp, 68-pin plcc, and 64-pin dip packages.
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-2 p r e l i m i n a r y ds971800401 notes: all signals with a preceding front slash, ??are ac- tive low, for example, b//w (word is active low); /b/w (byte is active low, only). alternatively, an overslash may be used to signify active low, for example wr power connections follow conventional descriptions be- low: connection circuit device power v cc v dd ground gnd v ss figure 1. z80180/z8s180/z8l180 functional block diagram 16-bit programmable reload timers (2) clocked serial i/o port mmu bus state control cpu interrupt /reset /rd /wr /m1 /mreq iorq /halt /wait /busreq /busack /rfsh st e /nmi int0 int1 int2 txs rxs/cts1 cks a18/tout dmac s (2) asynchronous sci (channel 0) asynchronous sci (channel 1) /dreq1 tend1 txa0 cka0, /dreq0 rxa0 /rts0 /cts0 /dcd0 txa1 cka1, /tend0 rxa1 timing generator xtal extal ? data buffer address buffer vcc vss a19-a0 d7-d0 data bus (8-bit) address bus (16-bit)
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-3 1 pin description figure 2. z80180 64-pin dip pin con?uration vss xtal extal /wait /busack /busreq /reset /nmi /int0 /int1 /int2 st a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18/tout vcc phi /rd /wr /m1 e /mreq /iorq /rfsh /halt /tend1 /dreq cks rxs//cts txs cka1//tend0 rxa1 txa1 cka//dreq0 rxa0 txa0 /dcd0 /cts0 /rts0 d7 d6 d5 d4 d3 d2 d1 d0 vss 33 64 z80180 64- pin dip 32 1
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-4 p r e l i m i n a r y ds971800401 figure 3. z80180/z8s180/z8l180 68-pin plcc pin con?uration 60 10 /int0 /int1 /int2 st a0 a1 a2 a3 vss a4 a5 a6 a7 a8 a9 a10 a11 /nmi /reset /busreq /busack /wait extal xtal vss vss phi /rd /wr /m1 e /mreq /iorq /rfsh 43 27 61 9 z80180/z8s180/ z8l180 68-pin plcc 1 /halt /tend1 /dreq1 cks rxs//cts1 txs cka1//tend0 rxa1 test txa1 cka0//dreq0 rxa0 txa0 /dcd0 /cts0 /rts0 d7 a12 a13 a14 a15 a16 a17 a18/tout vcc a19 vss d0 d1 d2 d3 d4 d5 d6
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-5 1 figure 4. z80180/z8s180/z8l180 80-pin qfp pin con?uration 40 65 /iorq /mreq e /m1 /wr /rd phi vss vss xtal n/c extal /wait /busack /busreq /reset /nmi n/c n/c /int0 /int1 /int2 st a0 a1 a2 a3 vss a4 n/c a5 a6 a7 a8 a9 a10 a11 n/c n/c a12 /rfsh n/c n/c /halt /tend1 /dreq1 cks rxs/cts1 txs cka1//tend0 rxa1 test txa1 n/c cka0//dreq0 rxa0 txa0 /dcd0 /cts0 /rts0 d7 n/c n/c d6 5101520 24 60 55 50 45 41 64 z80180/z8s180/z8l180 80-pin qfp 1 d5 d4 d3 d2 d1 d0 vss a19 vcc a18/tout nc a17 a16 a15 a14 a13
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-6 p r e l i m i n a r y ds971800401 table 1. z80180/z8s180/z8l180 pin identi?ation pin number and package type default function secondary function control qfp plcc dip 1 9 8 /nmi 2nc 3nc 4 10 9 /int0 5 11 10 /int1 6 12 11 /int2 71312 st 81413 a0 91514 a1 10 16 15 a2 11 17 16 a3 12 18 v ss 13 19 17 a4 14 nc 15 20 18 a5 16 21 19 a6 17 22 20 a7 18 23 21 a8 19 24 22 a9 20 25 23 a10 21 26 24 a11 22 nc 23 nc 24 27 25 a12 25 28 26 a13 26 29 27 a14 27 30 28 a15 28 31 29 a16 29 32 30 a17 30 nc 31 33 31 a18 /t out bit 2 or bit 3 of tcr 32 34 32 v cc 33 35 a19 34 36 33 v ss 35 37 34 d0 36 38 35 d1 37 39 36 d2 38 40 37 d3 39 41 38 d4 40 42 39 d5 41 43 40 d6 42 nc 43 nc 44 44 41 d7 45 45 42 /rts0
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-7 1 46 46 43 /cts0 47 47 44 /dcd0 48 48 45 txa0 49 49 46 rxa0 50 50 47 cka0 /dreq0 bit 3 or bit 5 of dmode 51 nc 52 51 48 txa1 53 52 test 54 53 49 rxa1 55 54 50 cka1 /tend0 bit 4 of cntla1 56 55 51 txs 57 56 52 rxs /cts1 bit 2 of stat1 58 57 53 cks 59 58 54 /dreq1 60 59 55 /tend1 61 60 56 /halt 62 nc 63 nc 64 61 57 /rfsh 65 62 58 /iorq 66 63 59 /mreq 67 64 60 e 68 65 61 m1 69 66 62 /wr 70 67 63 /rd 71 68 64 phi 72 1 1 v ss 73 2 v ss 74 3 2 xtal 75 nc 76 4 3 extal 77 5 4 /wait 78 6 5 /busack 79 7 6 /busreq 80 8 7 /reset table 1. z80180/z8s180/z8l180 pin identi?ation pin number and package type default function secondary function control qfp plcc dip
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-8 p r e l i m i n a r y ds971800401 table 2. pin status during reset busack and sleep pin number and package type pin status qfp plcc dip default function secondary function reset busack sleep 1 9 8 /nmi in in in 2nc 3nc 4 10 9 /int0 in in in 5 11 10 /int1 in in in 6 12 11 /int2 in in in 71312st 1?1 81413a0 3t 3t 1 91514a1 3t 3t 1 10 16 15 a2 3t 3t 1 11 17 16 a3 3t 3t 1 12 18 v ss gnd gnd gnd 13 19 17 a4 3t 3t 1 14 nc 15 20 18 a5 3t 3t 1 16 21 19 a6 3t 3t 1 17 22 20 a7 3t 3t 1 18 23 21 a8 3t 3t 1 19 24 22 a9 3t 3t 1 20 25 23 a10 3t 3t 1 21 26 24 a11 3t 3t 1 22 nc 23 nc 24 27 25 a12 3t 3t 1 25 28 26 a13 3t 3t 1 26 29 27 a14 3t 3t 1 27 30 28 a15 3t 3t 1 28 31 29 a16 3t 3t 1 29 32 30 a17 3t 3t 1 30 nc 31 33 31 a18 /t out 3t 3t 1 32 34 32 v cc v cc v cc v cc 33 35 a19 3t 3t 1 34 36 33 v ss gnd gnd gnd 35 37 34 d0 3t 3t 3t 36 38 35 d1 3t 3t 3t 37 39 36 d2 3t 3t 3t 38 40 37 d3 3t 3t 3t 39 41 38 d4 3t 3t 3t 40 42 39 d5 3t 3t 3t 41 43 40 d6 3t 3t 3t 42 nc 43 nc 44 44 41 d7 3t 3t 3t
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-9 1 45 45 42 /rts0 1 out 1 46 46 43 /cts0 in out in 47 47 44 /dcd0 in in in 48 48 45 txa0 1 out out 49 49 46 rxa0 in in in 50 50 47 cka0 /dreq0 3t out out 51 nc 52 51 48 txa1 1 out out 53 52 test 54 53 49 rxa1 in in in 55 54 50 cka1 /tend0 3t in in 56 55 51 txs 1 out out 57 56 52 rxs /cts1 in in in 58 57 53 cks 3t i/o i/o 59 58 54 /dreq1 in 3t in 60 59 55 /tend1 1 out 1 61 60 56 /halt 1 1 0 62 nc 63 nc 64 61 57 /rfsh 1 out out 65 62 58 /iorq 1 3t 1 66 63 59 /mreq 1 3t 1 67 64 60 e 0 out out 68 65 61 /m1 1 1 1 69 66 62 /wr 1 3t 1 70 67 63 /rd 1 3t 1 71 68 64 phi out out out 72 1 1 v ss gnd gnd gnd 73 2 v ss gnd gnd gnd 74 3 2 xtal out out out 75 nc 76 4 3 extal in in in 77 5 4 /wait in in in 78 6 5 /busack 1 out out 79 7 6 /busreq in in in 80 8 7 /reset in in in table 2. pin status during reset busack and sleep pin number and package type pin status qfp plcc dip default function secondary function reset busack sleep
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-10 p r e l i m i n a r y ds971800401 pin descriptions a0-a19. address bus (output, active high, tri-state). a0- a19 form a 20-bit address bus. the address bus provides the address for memory data bus exchanges, up to 1 mb, and i/o data bus exchanges, up to 64k. the address bus enters a high-impedance state during reset and external bus acknowledge cycles. address line a18 is multiplexed with the output of prt channel 1 (t out , selected as ad- dress output on reset) and address line a19 is not avail- able in dip versions of the z80180. busack. bus acknowledge (output, active low). /busack indicated the requesting device, the mpu ad- dress and data bus, and some control signals, have en- tered their high-impedance state. /busreq. bus request (input, active low). this input is used by external devices (such as dma controllers) to re- quest access to the system bus. this request has a higher priority than /nmi and is always recognized at the end of the current machine cycle. this signal will stop the cpu from executing further instructions and places address and data buses, and other control signals, into the high-imped- ance state. cka0, cka1. asynchronous clock 0 and 1 (bidirectional, active high). when in output mode, these pins are the transmit and receive clock outputs from the asci baud rate generators. when in input mode, these pins serve as the external clock inputs for the asci baud rate genera- tors. cka0 is multiplexed with /dreq0, and cka1 is mul- tiplexed with /tend0. cks. serial clock (bidirectional, active high). this line is clock for the csio channel. phi clock. system clock (output, active high). the out- put is used as a reference clock for the mpu and the ex- ternal system. the frequency of this output is equal to one- half that of the crystal or input clock frequency. /cts0 - /cts1. clear to send 0 and 1 (inputs, active low). these lines are modem control signals for the asci chan- nels. /cts1 is multiplexed with rxs. d0 - d7. data bus = (bidirectional, active high, tri-state). d0 - d7 constitute an 8-bit bi-directional data bus, used for the transfer of information to and from i/o and memory de- vices. the data bus enters the high-impedance state dur- ing reset and external bus acknowledge cycles. dcd0. data carrier detect 0 (input, active low). this is a programmable modem control signal for asci channel 0. /dreq0, /dreq1. dma request 0 and 1 (input, active low). /dreq is used to request a dma transfer from one of the on-chip dma channels. the dma channels monitor these inputs to determine when an external device is ready for a read or write operation. these inputs can be pro- grammed to be either level or edge sensed. /dreq0 is multiplexed with cka0. e. enable clock (output, active high). synchronous ma- chine cycle clock output during bus transactions. extal. external clock crystal (input, active high). crys- tal oscillator connections. an external clock can be input to the z80180/z8s180/z8l180 on this pin when a crystal is not used. this input is schmitt triggered. /halt. halt/sleep (output, active low). this output is asserted after the cpu has executed either the halt or slp instruction, and is waiting for either non-maskable or maskable interrupt before operation can resume. it is also used with the /m1 and st signals to decode status of the cpu machine cycle. /int0. maskable interrupt request 0 (input, active low). this signal is generated by external i/o devices. the cpu will honor these requests at the end of the current instruc- tion cycle as long as the /nmi and /busreq signals are inactive. the cpu acknowledges this interrupt request with an interrupt acknowledge cycle. during this cycle, both the /m1 and /iorq signals will become active. /int1, /int2. maskable interrupt request 1 and 2 (inputs, active low). this signal is generated by external i/o devic- es. the cpu will honor these requests at the end of the current instruction cycle as long as the /nmi, /busreq, and /int0 signals are inactive. the cpu will acknowledge these requests with an interrupt acknowledge cycle. unlike the acknowledgment for /int0, during this cycle neither the /m1 or /iorq signals will become active. /iorq. i /o request (output, active low, tri-state). / iorq indicates that the address bus contains a valid i/o address for an i/o read or i/o write operation. /iorq is also gener- ated, along with /m1, during the acknowledgment of the /int0 input signal to indicate that an interrupt response vector can be place onto the data bus. this signal is anal- ogous to the /ioe signal of the z64180. /m1. machine cycle 1 (output, active low). together with /mreq, /m1 indicates that the current cycle is the opcode fetch cycle of and instruction execution. together with /iorq, /m1 indicates that the current cycle is for an inter- rupt acknowledge. it is also used with the /halt and st signal to decode status of the cpu machine cycle. this signal is analogous to the /lir signal of the z64180. /mreq. memory request (output, active low, tri-state). /mreq indicates that the address bus holds a valid ad- dress for a memory read or memory write operation. this signal is analogous to the /me signal of z64180.
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-11 1 /nmi. non-maskable interrupt (input, negative edge trig- gered). /nmi has a higher priority than /int and is always recognized at the end of an instruction, regardless of the state of the interrupt enable flip-flops. this signal forces cpu execution to continue at location 0066h. /rd. reopcoded (output, active low, tri-state). /rd indi- cated that the cpu wants to read data from memory or an i/o device. the addressed i/o or memory device should use this signal to gate data onto the cpu data bus. /rfsh. refresh (output, active low). together with /mreq, /rfsh indicates that the current cpu machine cycle and the contents of the address bus should be used for refresh of dynamic memories. the low order 8 bits of the address bus (a7 - a10) contain the refresh address. this signal is analogous to the /ref signal of the z64180. /rts0. request to send 0 (output, active low). this is a programmable modem control signal for asci channel 0. rxa0, rxa1. receive data 0 and 1 (input, active high). these signals are the receive data to the asci channels. rxs. clocked serial receive data (input, active high). this line is the receiver data for the csio channel. rxs is multiplexed with the /cts1 signal for asci channel 1. st. status (output, active high). this signal is used with the /m1 and /halt output to decode the status of the cpu machine cycle. /tend0, /tend1. transfer end 0 and 1 (outputs, active low). this output is asserted active during the last write cycle of a dma operation. it is used to indicate the end of the block transfer. /tend0 is multiplexed with cka1. test. test (output, not in dip version). this pin is for test and should be left open. tout. timer out (output, active high). t out is the pulse output from prt channel 1. this line is multiplexed with a18 of the address bus. txa0, txa1. transmit data 0 and 1 (outputs, active high). these signals are the transmitted data from the asci channels. transmitted data changes are with re- spect to the falling edge of the transmit clock. txs. clocked serial transmit data (output, active high). this line is the transmitted data from the csio channel. /wait. wait (input, active low). /wait indicated to the mpu that the addressed memory or i/o devices are not ready for a data transfer. this input is sampled on the fall- ing edge of t2 (and subsequent wait states). if the input is sampled low, then the additional wait states are inserted until the /wait input is sampled high, at which time execu- tion will continue. /wr. write (output, active low, tri-state). /wr indicated that the cpu data bus holds valid data to be stored at the addressed i/o or memory location. xtal. crystal (input, active high). crystal oscillator con- nection. this pin should be left open if an external clock is used instead of a crystal. the oscillator input is not a ttl level (reference dc characteristics). several pins are used for different conditions, depending on the circumstance. multiplexed pin descriptions table 3. status summary st /halt /m1 operation 0 1 0 cpu operation (1st opcode fetch) 1 1 0 cpu operation (2nd opcode and 3rd opcode fetch) 1 1 1 cpu operation (mc except for opcode fetch) 0 x 1 dma operation 0 0 0 halt mode 1 0 1 sleep mode (including system stop mode) notes: x = reserved mc = machine cycle a18 / /t out during reset, this pin is initialized as a18 pin. if either toc1 or toc0 bit of the timer control register (tcr) is set to 1, tout function is selected. if toc1 and toc0 are cleared to 0, a18 function is selected. cka0 / /dreq0 during reset, this pin is initialized as cka0 pin. if either dm1 or sm1 in dma mode register (dmode) is set to 1, /dreq0 function is always selected. cka1 / /tend0 during reset, this pin is initialized as cka1 pin. if cka1d bit in asci control register ch1 (cntla1) is set to 1, /tend0 function is selected. if cka1d bit is set to 0, cka1 function is selected. rxs / /cts1 during reset, this pin is initialized as rxs pin. if cts1e bit in asci status register ch1 (stat1) is set to 1, /cts 1 function is selected. if cts1e bit is set to 0, rxs function is selected.
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-12 p r e l i m i n a r y ds971800401 architecture the z180 combines a high-performance cpu core with a variety of system and i/o resources useful in a broad range of applications. the cpu core consists of five func- tional blocks: clock generator, bus state controller, inter- rupt controller, memory management unit (mmu), and the central processing unit (cpu). the integrated i/o resourc- es make up the remaining four function blocks: direct memory access (dma) control (2 channels), asynchro- nous serial communication interface (asci, 2 channels) programmable reload timers (prt, 2 channels), and a clock serial i/o (csio) channel. clock generator. generates system clock from an exter- nal crystal or clock input. the external clock is divided by two or one and provided to both internal and external de- vices. bus state controller. this logic performs all of the status and bus control activity associated with both the cpu and some on-chip peripherals. this includes wait-state timing, reset cycles, dram refresh, and dma bus exchanges. interrupt controller. this logic monitors and prioritizes the variety of internal and external interrupts and traps to provide the correct responses from the cpu. to maintain compatibility with the z80 cpu, three different interrupts modes are supported. memory management unit. the mmu allows the user to ?ap?the memory used by the cpu (logically only 64kb) into the 1 mb addressing range supported by the z80180/z8s180/z8l180. the organization of the mmu object code maintains compatibility with the z80 cpu, while offering access to an extended memory space. this is accomplished by using an effective ?ommon area- banked area?scheme. central processing unit. the cpu is microcoded to pro- vide a core that is object-code compatible with the z80 cpu. it also provides a superset of the z80 instruction set, including 8-bit multiply. the core has been modified to al- low many of the instructions to execute in fewer clock cy- cles. dma controller. the dma controller provides high speed transfers between memory and i/o devices. transfer op- erations supported are memory-to-memory, memory to/from i/o, and i/o-to-i/o. transfer modes supported are request, burst, and cycle steal. dma transfers can access the full 1 mb address range with a block length up to 64 kb, and can cross over 64k boundaries. asynchronous serial communication interface (as- ci). the asci logic provides two individual full-duplex uarts. each channel includes a programmable baud rate generator and modem control signals. the asci channels can also support a multiprocessor communication format as well as break detection and generation. programmable reload timers (prt). this logic consists of two separate channels, each containing a 16-bit counter (timer) and count reload register. the time base for the counters is derived from the system clock (divided by 20) before reaching the counter. prt channel 1 provides an optional output to allow for waveform generation.
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-13 1 figure 5. timer initialization, count down, and reload timing ffffh 0004h 0003h 0002h 0001h 0000h 0003h 0002h 0001h 0000h 0003h timer data register write (0004h) timer data register timer reload register tde flag tif flag reset 20 f 20 f 20 f 20 f 20 f 20 f 20 f 20 f 20 f 0 < t < 20 f timer reload register write (0003h) ffffh 0003h reload reload write ??to tde timer data register read timer control requestor read figure 6. timer output timing timer data reg. = 0001h timer data reg. = 0000h tout f
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-14 p r e l i m i n a r y ds971800401 clocked serial i/o (csi/o). the csio channel provides a half-duplex serial transmitter and receiver. this channel can be used for simple high-speed data connection to an- other microprocessor or microcomputer . trdr is used for both csi/o transmission and reception. thus, the system design must ensure that the constraints of half-duplex op- eration are met (transmit and receive operation cannot occur simultaneously). for example, if a csi/o transmis- sion is attempted while the csi/o is receiving data, a csi/o will not work. also note that trdr is not buffered. therefore, attempting to perform a csi/o transmit while the previous transmit data is still being shifted out causes the shift data to be immediately updated, thereby corrupt- ing the transmit operation in progress. similarly, reading trdr while a transmit or receive is in progress should be avoided. operation modes z80 versus 64180 compatibility. the z80180/z8s180/z8l180 is descended from two different ?ncestor?processors, zilog's original z80 and the hitachi 64180. the operating mode control register (omcr), shown in figure 8, can be programmed to select between certain z80 and 64180differences. m1e (m1 enable). this bit controls the m1 output and is set to a 1 during reset. when m1e=1, the m1 output is asserted low during the opcode fetch cycle, the int0 acknowledge cycle, and the first machine cycle of the nmi acknowledge. on the z80180/z8s180/z8l180, this choice makes the processor fetch an reti instruction once, and when fetch- ing an reti from zero-wait-state memory will use three clock machine cycles, which are not fully z80-timing com- patible but are compatible with the on-chip ctcs. when m1e=0, the processor does not drive m1 low during instruction fetch cycles, and after fetching an reti instruc- tion once with normal timing, it goes back and re-fetches the instruction using fully z80-compatible cycles that in- clude driving m1 low. this may be needed by some exter- nal z80 peripherals to properly decode the reti instruc- tion. figure 9 and table 4 show the reti sequence when m1e=0. figure 7. csio block diagram internal address/data bus csi/o transmit/receive data register: trdr (8) csi/o control register: cntr (8) baud rate generator txs rxs cks f interrupt request figure 8. operating control register (omcr: i/o address = 3eh) d7 reserved d6 d5 -- m1e (r/w) -- -- -- -- /ioc (r/w) /m1te (w)
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-15 1 m1te (m1 temporary enable). this bit controls the tem- porary assertion of the /m1 signal. it is always read back as a 1 and is set to 1 during reset. when m1e is set to 0 to accommodate certain external z80 peripheral(s), those same device(s) may require a pulse on m1 after programming certain of their registers to complete the function being programmed. for example, when a control word is written to the z80 pio to enable interrupts, no enable actually takes place until the pio sees an active m1 signal. when m1te=1, there is no change in the operation of the /m1 signal and m1e con- trols its function. when m1te=0, the m1 output will be as- serted during the next opcode fetch cycle regardless of the state programmed into the m1e bit. this is only momen- tary (one time) and the user need not preprogram a 1 to disable the function (see figure10). figure 9. reti instruction sequence with mie=0 t 1 t 2 t 3 t 1 t 2 t 3 t i t i t i t 1 t 2 t 3 t 1 t 2 t 3 t i t i a 0 -a 18 (a 19 ) f d 0 -d 7 pc pc+1 pc pc+1 edh 4dh edh 4dh mreq m1 rd st table 4. reti control signal states with mie=0 machine m1 cycle states address data rd wr mreq iorq ioc=1 ioc=0 halt st 1 t1-t3 1st opcode edh 0 1 0 1 0 1 1 0 2 t1-t3 2nd opcode 4dh 0 1 0 1 0 1 1 0 ti na tri-state 1 1 1 1 1 1 1 1 ti na tri-state 1 1 1 1 1 1 1 1 ti na tri-state 1 1 1 1 1 1 1 1 3 t1-t3 1st opcode edh 0 1 0 1 0 0 1 1 ti na tri-state 1 1 1 1 1 1 1 1 4 t1-t3 2nd opcode 4dh 0 1 0 1 0 1 1 1 5 t1-t3 sp data 0 1 0 1 1 1 1 1 6 t1-t3 sp+1 data 0 1 0 1 1 1 1 1
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-16 p r e l i m i n a r y ds971800401 ioc. this bit controls the timing of the /iorq and /rd sig- nals. it is set to 1 by reset. when /ioc=1, the /iorq and /rd signals function the same as the z64180 (figure 11). when /ioc = 0, the timing of the /iorq and rd signals match the timing of the z80. the /iorq and /rd signals go active as a result of the rising edge of t2. (figure 12.) figure 10. m1 temporary enable timing t 1 t 2 t 3 t 1 t 2 t 3 f /wr /m1 opcode fetch write into omcr figure 11. i/o read and write cycles with ioc = 1 t 1 t 2 t w t 3 f /iorq /rd /wr figure 12. i/o read and write cycles with ioc = 0 t 1 t 2 t w t 3 f /iorq /rd /wr
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-17 1 halt and low-power operating modes. the z80180/z8s180/z8l180 can operate in seven modes with respect to activity and power consumption: normal operation halt mode iostop mode sleep mode system stop mode idle mode standby mode (with or without quick recovery) normal operation. the z80180/z8s180/z8l180 proces- sor is fetching and running a program. all enabled func- tions and portions of the device are active, and the halt pin is high. halt mode. this mode is entered by the halt instruc- tion. thereafter, the z80180/z8s180/z8l180 processor continually fetches the following opcode but does not exe- cute it, and drives the halt, st and m1 pins all low. the oscillator and phi pin remain active, interrupts and bus granting to external masters, and dram refresh can occur and all on-chip i/o devices continue to operate including the dma channels. the z80180/z8s180/z8l180 leaves halt mode in re- sponse to a low on reset, on to an interrupt from an en- abled on-chip source, an external request on nmi, or an enabled external request on int0, int1, or int2. in case of an interrupt, the return address will be the instruction fol- lowing the halt instruction; at that point the program can either branch back to the halt instruction to wait for an- other interrupt, or can examine the new state of the sys- tem/application and respond appropriately. sleep mode. this mode is entered by keeping the iostop bit (icr5) bits 3 and 6 of the cpu control regis- ter (ccr3, ccr6) all zero and executing the slp instruc- tion. the oscillator and phi output continue operating, but are blocked from the cpu core and dma channels to re- duce power consumption. dram refresh stops but inter- rupts and granting to external master can occur. except when the bus is granted to an external master, a19-0 and all control signals except /halt are maintained high. /halt is low. i/o operations continue as before the slp instruction, except for the dma channels. the z80180/z8s180/z8l180 leaves sleep mode in re- sponse to a low on /reset, an interrupt request from an on-chip source, an external request on /nmi, or an external request on /int0, 1, or 2. figure 13. halt timing int i , nmi a 0 -a 19 /halt /m1 /mreq /rd halt opcode address halt opcode address + 1
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-18 p r e l i m i n a r y ds971800401 if an interrupt source is individually disabled, it cannot bring the z80180/z8s180/z8l180 out of sleep mode. if an interrupt source is individually enabled, and the ief bit is 1 so that interrupts are globally enabled (by an ei in- struction), the highest priority active interrupt will occur, with the return address being the instruction after the slp instruction. if an interrupt source is individually enabled, but the ief bit is 0 so that interrupts are globally disabled (by a di instruction), the z80180/z8s180/z8l180 leaves sleep mode by simply executing the following instruc- tion(s). this provides a technique for synchronization with high- speed external events without incurring the latency im- posed by an interrupt response sequence. figure 14 shows the timing for exiting sleep mode due to an inter- rupt request. note that the z80180/z8s180/z8l180 takes about 1.5 clocks to restart. iostop mode. iostop mode is entered by setting the iostop bit of the i/o control register (icr) to 1. in this case, on-chip i/o (asci, csi/o, prt) stops operating. however, the cpu continues to operate. recovery from iostop mode is by resetting the iostop bit in icr to 0. system stop mode . system stop mode is the com- bination of sleep and iostop modes. system stop mode is entered by setting the iostop bit in icr to 1 fol- lowed by execution of the slp instruction. in this mode, on-chip i/o and cpu stop operating, reducing power con- sumption, but the phi output continues to operate. recov- ery from system stop mode is the same as recovery from sleep mode except that internal i/o sources (dis- abled by iostop) cannot generate a recovery interrupt. idle mode. software can put the z80180/z8s180/z8l180 into this mode by setting the iostop bit (icr5) to 1, ccr6 to 0, ccr3 to 1 and exe- cuting the slp instruction. the oscillator keeps operating but its output is blocked to all circuitry including the phi pin. dram refresh and all internal devices stop, but exter- nal interrupts can occur. bus granting to external masters can occur if the brest bit in the cpu control register (ccr5) was set to 1 before idle mode was entered. the z80180/z8s180/z8l180 leaves idle mode in re- sponse to a low on reset, an external interrupt request on nmi, or an external interrupt request on /int0, /int1 or /int2 that is enabled in the int/trap control register. as previously described for sleep mode, when the z80180/z8s180/z8l180 leaves idle mode due to an nmi, or due to an enabled external interrupt request when the ief flag is 1 due to an ei instruction, it starts by per- forming the interrupt with the return address being that of the instruction after the slp instruction. if an external interrupt enables the int/trap control reg- ister while the ief1 bit is 0, z80180/z8s180/z8l180 leaves idle mode; specifically, the processor restarts by executing the instructions following the slp instruction. figure 14. sleep timing slp 2nd opcode sleep mode f t 2 t 3 t 1 t 2 t s t s t 1 /inti, /nmi a 0 -a 19 /halt m1 opcode fetch or interrupt acknowledge cycle slp 2nd opcode address fffffh fetch cycle t 2 t 3
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-19 1 figure 15 shows the timing for exiting idle mode due to an interrupt request. note that the z80180/z8s180/z8l180 takes about 9.5 clocks to restart. while the z80180/z8s180/z8l180 is in idle mode, it will grant the bus to an external master if the brext bit (ccr5) is 1. figure 16 shows the timing for this sequence. note that the part takes 8 clock cycles longer to respond to the bus request than in normal operation. after the external master negates the bus request, the z80180/z8s180/z8l180 disables the phi clock and re- mains in idle mode. figure 15. z80180/z8s180/z8l180 idle mode exit due to external interrupt f t 1 t 2 t 4 nmi a 19 -a 0 halt m1 opcode fetch or interrupt acknowledge cycle fffffh idle mode t 3 9.5 cycle delay from inti asserted inti or
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-20 p r e l i m i n a r y ds971800401 standby mode (with or without quick recovery). software can put the z80180/z8s180/z8l180 into this mode by setting the iostop bit (icr5) to 1 and ccr6 to 1, and executing the slp instruction. this mode stops the on-chip oscillator and thus draws the least power of any mode, less than 10 mm a. as with idle mode, the z80180/z8s180/z8l180 will leave standby mode in response to a low on reset or on nmi , or a low on int0 -2 that is enabled by a 1 in the cor- responding bit in the int/trap control register, and will grant the bus to an external master if the brext bit in the cpu control register (ccr5) is 1. but the time required for all of these operations is greatly increased by the need to restart the on-chip oscillator and ensure that it has sta- bilized to square-wave operation. when an external clock is connected to the extal pin rather than a crystal to the xtal and extal pins, and the external clock runs continuously, there is little need to use standby mode because there is no time required to re- start the oscillator, and other modes restart faster. howev- er, if external logic stops the clock during standby mode (for example, by decoding halt low and m1 high for sev- eral clock cycles), then standby mode can be useful to allow the external clock source to stabilize after it is re-en- abled. when external logic drives reset low to being a z80180/z8s180/z8l180 out of standby mode, and a crystal is used or an external clock source has been stopped, the external logic must hold reset low until the on-chip oscillator or external clock source has restarted and stabilized. the clock stability requirements of the z80180/z8s180/z8l180 are much less in the divide-by- two mode that's selected by a reset sequence and there- after controlled by the clock divide bit in the cpu control register (ccr7). because of this, software should: a. program ccr7 to 0 to select divide-by-two mode, before the slp instruction that enters standby mode, and. b. after a reset, interrupt or in-line restart after the slp 01 instruction, delay programming ccr7 back to 1 to set divide-by-one mode, as long as possible to allow additional clock stabilization time. if software sets ccr6 to 1 before the slp instruction plac- es the mpu in standby mode, the value in the ccr3 bit determines how long the z80180/z8s180/z8l180 will wait for oscillator restart and stabilization when it leaves standby mode due to an external interrupt request. if ccr3 is 0, the z80180/z8s180/z8l180 waits 217 (131,072) clock cycles, while if ccr3 is 1, it waits only 64 clock cycles. the latter is called quick recovery mode. the same delay applies to granting the bus to an figure 16. bus granting to external master in idle mode f tx busreq a 19 -a 0 halt m1 bus release mode idle mode fffffh idle mode 9.5 cycle delay until busack asserted busack tx high impedance fffffh high low
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-21 1 external master during standby mode, when the brext bit in the cpu control register (ccr5) is 1. as described previously for sleep and idle modes, when a z80180/z8s180/z8l180 leaves standby mode due to nmi low, or when it leaves standby mode due to an enabled into -2 low when the ief, flag is 1 due to an ie instruction, it starts by performing the interrupt with the return address being that of the instruction following the slp instruction. if the z80180/z8s180/z8l180 leaves standby mode due to an external interrupt request that's enabled in the int/trap control register, but the ief, bit is 0 due to a di instruction, the processor restarts by exe- cuting the instruction(s) following the slp instruction. if int0 , or int1 or 2 goes inactive before the end of the clock stabilization delay, the z80180/z8s180/z8l180 stays in standby mode. figure 17 shows the timing for leaving standby mode due to an interrupt request. note that the z80180/z8s180/z8l180 takes either 64 or 217 (131,072) clocks to restart, depending on the ccr3 bit. while the z80180/z8s180/z8l180 is in standby mode, it will grant the bus to an external master if the brext bit (ccr5) is 1. figure 18 shows the timing of this sequence. note that the part takes 64 or 217 (131,072) clock cycles to grant the bus depending on the ccr3 bit. the latter (non-quick-recovery) case may be prohibitive for many ?emand driven?external masters. if so, quick recovery or idle mode can be used. figure 17. z80180/z8s180/z8l180 standby mode exit due to external interrupt f t 1 t 2 t 4 nmi a 19 -a 0 halt m1 opcode fetch or interrupt acknowledge cycle fffffh standby mode t 3 2 17 or 64 cycle delay from inti asserted inti or
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-22 p r e l i m i n a r y ds971800401 figure 18. bus granting to external master during standby mode f tx tx busreq a 19 -a 0 halt m1 standby mode bus release mode fffffh standby mode 64 or 2 17 cycle delay after busreq asserted busack fffffh low high
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-23 1 standard test conditions the dc characteristics and capacitance sections above apply to the following standard test conditions, unless oth- erwise noted. all voltages are referenced to gnd (0v). positive current flows in to the referenced pin. all ac parameters assume a load capacitance of 100 pf. add 10 ns delay for each 50 pf increase in load up to a maximum of 200 pf for the data bus and 100 pf for the ad- dress and control lines. ac timing measurements are ref- erenced to 1.5 volts (except for clock, which is refer- enced to the 10% and 90% points). the ordering information section lists temperature ranges and product numbers. package drawings are in the package informa- tion section. refer to the literature list for additional doc- umentation. absolute maximum ratings note: permanent lsi damage may occur if maximum ratings are exceeded. normal operation should be under recommended operating conditions. if these conditions are exceeded, it could affect reliability of lsi. figure 19. ac load capacitance parameters +5 v from output 100 pf under test 250 m a 2.1k item symbol value unit supply voltage v cc -0.3 ~ +7.0 v input voltage v in -0.3 ~ v cc +0.3 v operating temperature t opr 0 ~ 70 c extended temperature t ext -40 ~ 85 c storage temperature t stg -55 ~ +150 c
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-24 p r e l i m i n a r y ds971800401 dc characteristics note: v cc = 5v + 10%, v ss = 0v over specified temperature range unless otherwise noted. symbol item condition min. typ. max. unit v ih1 input ? voltage /reset, extal, /nmi v cc -0.6 v cc +0.3 v v ih2 input ? voltage except /reset, extal, /nmi 2.0 v cc +0.3 v v ih3 input ? voltage except cks, cka0, cka1 2.4 v cc +0.3 v v il1 input ? voltage /reset, extal, /nmi -0.3 0.6 v v il2 input ? voltage except /reset, extal, /nmi -0.3 0.8 v v oh outputs ? voltage all outputs i oh = -200 m a 2.4 v i oh = -20 m av cc -1.2 v ol outputs ? voltage all outputs i ol = -2.2 m a 0.45 v i il input leakage current all inputs except xtal, extal v in = 0.5 ~ v cc -0.5 1.0 m a i tl three state leakage current v in = 0.5 ~ v cc -0.5 1.0 m a i cc * power dissipation* (normal operation) f = 6 mhz 15 40 ma f = 8 mhz 20 50 f = 10 mhz** 25 60 power dissipation* (system stop mode) f = 6 mhz 3.8 12.5 f = 8 mhz 5 15 f = 10 mhz** 6.3 17.5 c p pin capacitance v in = 0 v , f = 1 mhz ta = 25 c 12 pf note: ** v ihmin = v cc -1.0v, v ilmax = 0.8v (all output terminals are at no load.) v cc = 5.0v
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-25 1 ac characteristics v cc = 5v + 10%, v ss = 0v, t a - 0 to +70 c, unless otherwise noted. no. symbol item z80180-6 z80180-8 z80180-10 unit min. max. min. max. min. max. 1. t cyc clock cycle time 162 2000 125 2000 100 2000 ns 2. t chw clock ? pulse width 65 50 40 ns 3. t clw clock ? pulse width 65 50 40 ns 4. t cf clock fall time 15 15 10 ns 5. t cr clock rise time 15 15 10 ns 6. t ad rise to address valid delay 90 80 70 ns 7. t as address valid to /mreq fall or /iorq fall) 30?0?0ns 8. t med1 fall to /mreq fall delay ?0?0?0ns 9. t rdd1 fall to /rd fall delay /ioc = 1 ?0?0?0ns rise to /rd rise delay /ioc = 0 ?5?0?5 10. t m1d1 rise to /m1 fall delay ?0?0?0ns 11. t ah address hold time from (/mreq, /ioreq, /rd, /wr) 35?0?0ns 12. t med2 fall to /mreq rise delay ?0?0?0ns 13. t rdd2 fall to /rd rise delay ?0?0?0ns 14. t m1d2 rise to /m1 rise delay ?070*?0ns 15. t drs data read set-up time 40 30 25 ns 16. t drh data read hold time 0??ns 17. t std1 fall to st fall delay ?0?0?0ns 18. t std2 fall to st rise delay ?0?0?0ns 19. t ws /wait set-up time to fall 40 40 30 ns 20. t wh /wait hold time from fall 40 40 30 ns 21. t wdz rise to data float delay 95 70 60 ns 22. t wrd1 rise to /wr fall delay ?5?0?0ns 23. t wdd fall to write data delay time 90 80 60 ns 24. t wds write data set-up time to /wr fall 40 20 15 ns 25. t wrd2 fall to /wr rise delay ?0?0?0ns 26. t wrp /wr pulse width 170 130 110 ns 26a. /wr pulse width (i/o write cycle) 332 255 210 ns 27. t wdh write data hold time from (/wr rise ) 40?5?0 28. t iod1 fall to /iorq fall delay /ioc = 1 ?0?0?0ns rise to /iorq fall delay /ioc = 1 ?5?0?5 29. t iod2 fall to /iorq rise delay ?0?0?0ns 30. t iod3 /m1 fall to /iorq fall delay 340 250 200 ns 31. t ints /int set-up time to fall 40 40 30 ns 32. t ints /int hold time from fall 40 40 30 ns 33. t nmiw /nmi pulse width 120 100 80 ns 34. t brs /busreq set-up time to fall 40 40 30 ns 35. t brh /busreq hold time from fall 40 40 30 ns 36. t bad1 rise to /busack fall delay ?5?0?0ns 37. t bad2 fall to /busack rise delay ?0?0?0ns 38. t bzd rise to bus floating delay time 125 90 80 ns 39. t mewh /mreq pulse width (high) 110 90 70 ns
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-26 p r e l i m i n a r y ds971800401 40. t mewl /mreq pulse width (low) 125 100 80 ns 41. t rfd1 rise to /rfsh fall delay 90 80 60 ns 42. t rfd2 rise to /rfsh rise delay 90 80 60 ns 43. t had1 rise to /halt fall delay 90 80 50 ns 44. t had2 rise to /halt rise delay 90 80 50 ns 45. t drqs /dreqi set-up time to rise 40 40 30 ns 46. t drqh /dreqi hold time from rise 40 40 30 ns 47. t ted1 fall to /tendi fall delay 70 60 50 ns 48. t ted2 fall to /tendi rise delay 70 60 50 ns 49. t ed1 rise to e rise delay 95 70 60 ns 50. t ed2 fall or rise to e fall delay 95 70 60 ns 51. p weh e pulse width (high) 75 65 55 ns 52. p wel e pulse width (low) 180 130 110 ns 53. t er enable rise time 20 20 20 ns 54. t ef enable fall time 20 20 20 ns 55. t tod fall to timer output delay 300 200 150 ns 56. t stdi csi/o transmit data delay time (internal clock operation) 200 200 150 ns 57. t stde csi/o transmit data delay time (external clock operation) 7.5tcyc +300 7.5tcyc +200 7.5tcyc +150 ns 58. t srsi csi/o receive data set-up time (internal clock operation) 1?? tcyc 59. t srhi csi/o receive data hold time (internal clock operation) 1?? tcyc 60. t srse csi/o receive data set-up time (external clock operation) 1?? tcyc 61. t srhe csi/o receive data hold time (external clock operation) 1?? tcyc 62. t res /reset set-up time to fall 120 100 80 ns 63. t reh /reset hold time from fall 80 70 50 ns 64. t osc oscillator stabilization time 20 20 tbd ns 65. t exr external clock rise time (extal) 25 25 25 ns 66. t exf external clock fall time (extal) 25 25 25 ns 67. t rr /reset rise time 50 50 50 ns 68. t rf /reset fall time 50 50 50 ns 69. t ir input rise time (except extal, /reset) 100 100 100 ns 70. t if input fall time (except extal, /reset) 100 100 100 ns no. symbol item z80180-6 z80180-8 z80180-10 unit min. max. min. max. min. max.
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-27 1 ac characteristics (v cc = 5v 10% or v cc = 3.3v 10% over specified temperature range, unless otherwise noted, 33 mhz characteristics apply only to 5v operation.) no. symbol item z80180-20 z80180-33 unit min. max. min. max. 1. t cyc clock cycle time 50 2000 33 2000 ns 2. t chw clock ? pulse width 15 10 ns 3. t clw clock ? pulse width 15 10 ns 4. t cf clock fall time 10 5 ns 5. t cr clock rise time 10 5 ns 6. t ad rise to address valid delay 15 15 ns 7. t as address valid to /mreq fall or /iorq fall) 20 5 ns 8. t med1 fall to /mreq fall delay ?5?5ns 9. t rdd1 fall to /rd fall delay /ioc = 1 ?5?5ns rise to /rd rise delay /ioc = 0 ?5?5 10. t m1d1 rise to /m1 fall delay ?5?5ns 11. t ah address hold time from (/mreq, /ioreq, /rd, /wr) ?05 ns 12. t med2 fall to /mreq rise delay ?5?5ns 13. t rdd2 fall to /rd rise delay ?5?5ns 14. t m1d2 rise to /m1 rise delay 15 15* ns 15. t drs data read set-up time 15 15 ns 16. t drh data read hold time 0?ns 17. t std1 fall to st fall delay ?5?5ns 18. t std2 fall to st rise delay ?5?5ns 19. t ws /wait set-up time to fall 15 15 ns 20. t wh /wait hold time from fall 5?ns 21. t wdz rise to data float delay 10 10 ns 22. t wrd1 rise to /wr fall delay ?5?5ns 23. t wdd fall to write data delay time 20 20 ns 24. t wds write data set-up time to /wr fall 10 0 ns 25. t wrd2 fall to /wr rise delay ?5?5ns 26. t wrp /wr pulse width 70 40 ns 26a. /wr pulse width (i/o write cycle) 120 70 ns 27. t wdh write data hold time from (/wr rise ) 5? 28. t iod1 fall to /iorq fall delay /ioc = 1 ?5?5ns rise to /iorq fall delay /ioc = 1 ?5?5 29. t iod2 fall to /iorq rise delay ?5?5ns 30. t iod3 /m1 fall to /iorq fall delay 120 70 ns 31. t ints /int set-up time to fall 15 15 ns 32. t ints /int hold time from fall 10 10 ns 33. t nmiw /nmi pulse width 35 25 ns 34. t brs /busreq set-up time to fall 10 10 ns 35. t brh /busreq hold time from fall 10 10 ns 36. t bad1 rise to /busack fall delay ?5?5ns 37. t bad2 fall to /busack rise delay ?5?5ns
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-28 p r e l i m i n a r y ds971800401 38. t bzd rise to bus floating delay time 10 25 ns 39. t mewh /mreq pulse width (high) 45 25 ns 40. t mewl /mreq pulse width (low) 45 25 ns 41. t rfd1 rise to /rfsh fall delay 15 15 ns 42. t rfd2 rise to /rfsh rise delay 15 15 ns 43. t had1 rise to /halt fall delay 15 15 ns 44. t had2 rise to /halt rise delay 15 15 ns 45. t drqs /dreqi set-up time to rise 20 20 ns 46. t drqh /dreqi hold time from rise 15 15 ns 47. t ted1 fall to /tendi fall delay 15 15 ns 48. t ted2 fall to /tendi rise delay 15 15 ns 49. t ed1 rise to e rise delay 15 15 ns 50. t ed2 fall or rise to e fall delay 15 15 ns 51. p weh e pulse width (high) 45 20 ns 52. p wel e pulse width (low) 70 20 ns 53. t er enable rise time 10 10 ns 54. t ef enable fall time 10 10 ns 55. t tod fall to timer output delay 50 50 ns 56. t stdi csi/o transmit data delay time (internal clock operation) ??ns 57. t stde csi/o transmit data delay time (external clock operation) 7.5tcyc +75 7.5tcyc +60 ns 58. t srsi csi/o receive data set-up time (internal clock operation) 1? tcyc 59. t srhi csi/o receive data hold time (internal clock operation) 1? tcyc 60. t srse csi/o receive data set-up time (external clock operation) 1? tcyc 61. t srhe csi/o receive data hold time (external clock operation) 1? tcyc 62. t res /reset set-up time to fall 25 25 ns 63. t reh /reset hold time from fall 15 15 ns 64. t osc oscillator stabilization time 20 20 ns 65. t exr external clock rise time (extal) 10 5 ns 66. t exf external clock fall time (extal) 10 5 ns 67. t rr /reset rise time 50 50 ns 68. t rf /reset fall time 50 50 ns 69. t ir input rise time (except extal, /reset) 50 50 ns 70. t if input fall time (except extal, /reset) 50 50 ns no. symbol item z80180-20 z80180-33 unit min. max. min. max.
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-29 1 timing diagrams notes: *1. output buffer is off at this point. *2. memory read/write cycle timing are the same as i/o read/write cycle except there are no automatic wait states (t w ), and /mreq is active instead of /iorq. figure 20. cpu timing (opcode fetch cycle, memory read cycle, memory write cycle, i/o write cycle, i/o read cycle) address /wait /mreq /iorq /rd /wr /m1 st data in data out /reset 11 67 68 62 63 68 67 62 63 15 16 17 10 14 9 22 13 11 28 7 29 7 8 20 19 19 20 11 12 6 9 13 25 11 opcode fetch cycle t 1 1 2 3 4 5 15 16 21 27 * 1 18 i/o write cycle *2 i/o read cycle *2 t 2 t w t 3 t 1 t 2 t w t 3 t 1 23 24
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-30 p r e l i m i n a r y ds971800401 notes: 1. during /int 0 acknowledge cycle. 2. during refresh cycle. 3. output buffer is off at this point. figure 21. cpu timing (/int 0 acknowledge cycle, refresh cycle, bus release mode, halt mode, sleep mode, system stop mode) /inti 31 32 33 40 30 28 15 16 29 39 41 42 34 35 34 35 36 37 38 38 43 44 * 3 14 10 /nmi /mi *1 /iorq *1 date in *1 /mreq *2 /rfsh *2 /busreq /busack address data /mreq /rd /wr, /iorq /halt
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-31 1 figure 22. cpu timing (/ioc = 0) (i/o read cycle, i/o write cycle) 1. t drqs and t dhqh are specified for the rising edge of clock followed by t 3 . *2. t drqs and t dhqh are specified for the rising edge of clock. *3. dma cycle starts. *4. cpu cycle starts figure 23. dma control signals t 1 t 2 t w t 3 t 1 t 2 t w t 3 address f rd iroq wr 28 9 29 28 29 13 22 25 i/o read cycle i/o write cycle cpu timing (ioc=0) i/o read cycle i/o write cycle 47 45 46 48 18 * 4 * 2 (at level sense) /dreqi (at level sense) /tendi st t 1 t 2 t w t 3 t 1 * 3 17 /dreqi cpu or dma read/write cycle (only dma write cycle for /tendi) 45 46 * 1
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-32 p r e l i m i n a r y ds971800401 figure 24. e clock timing (memory read/write cycle, i/o read/write cycle) figure 25. e clock timing (bus release mode, sleep mode, system stop mode) figure 26. e clock timing (minimum timing example of p wel and p weh ) 49 49 49 15 50 50 50 16 d 0 - d 7 e (memory read//write) e (i/o read) e (i/o write) ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t 1 t 2 t w t w t 3 e bus release mode sleep mode system stop mode 49 50 50 52 53 49 53 t 2 t 2 t w t 3 t 1 54 49 51 54 50 e example i/o read ? opcode fetch
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-33 1 figure 27. timer output timing figure 28. slp execution cycle 55 timer data reg.=0000h a 18 /tout 32 44 43 33 a 0 ~ a 18 slp instruction fetch /mreq, /mi /nmi /int i /halt ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t 1 t 2 t s t s t 3 t 1 t 2 31 /rd next opcode fetch ~ ~ ~ ~
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-34 p r e l i m i n a r y ds971800401 figure 29. csi/o receive/transmit timing figure 30. rise time and fall times 57 56 58 56 11.5t cyc transmit data 59 58 59 11.5t cyc 11t cyc 16.5t cyc 11t cyc 16.5t cyc 57 60 61 60 61 (external clock) transmit data (internal clock) receive data (external clock) receive data (internal clock) csi/o clock 65 66 v il1 v ih1 extal v il1 v ih1 70 69 input rise time and fall time (except extal, /reset) external clock rise time and fall time
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-35 1 cpu control register cpu control register (ccr). this register controls the basic clock rate, certain aspects of power-down modes, and output drive/low noise options (figure 31). bit 7. clock divide select. if this bit is 0, as it is after a re- set, the z80180/z8s180/z8l180 divides the frequency on the xtal pin(s) by two to obtain its master clock phi. if this bit is programmed as 1, the part uses the xtal frequency as phi without division. if an external oscillator is used in divide-by-one mode, the minimum pulse width requirement given in the ac charac- teristics must be satisfied. bits 6 and 3. standby/idle control. when these bits are both 0, a slp instruction makes the z80180/z8s180/z8l180 enter sleep or system stop mode, depending on the iostop bit (icr5). when d6 is 0 and d3 is 1, setting the iostop bit (icr5) and executing a slp instruction puts the z80180/z8s180/z8l180 into idle mode in which the on- chip oscillator runs, but its output is blocked from the rest of the part, including phi out. when d6 is 1 and d3 is 0, setting iostop (icr5) and ex- ecuting a slp instruction puts the part into standby mode, in which the on-chip oscillator is stopped and the part allows 217 (128k) clock cycles for the oscillator to sta- bilize when it's restarted. when d6 and d3 are both 1, setting iostop (icr5) and executing a slp instruction puts the part into quick re- covery standby mode, in which the on-chip oscillator is stopped, and the part allows only 64 clock cycles for the oscillator to stabilize when it's restarted. the latter section, halt and low power modes, de- scribes the subject more fully. bit 5 brext. this bit controls the ability of the z8s180/z8l180 to honor a bus request during standby mode. if this bit is set to 1 and the part is in standby mode, a busreq is honored after the clock stabilization timer is timed out. bit 4 lnphi. this bit controls the drive capability on the phi clock output. if this bit is set to 1, the phi clock output will be reduced to 33 percent of its drive capability. figure 31. cpu control register (ccr) address 1fh d7 lnad/data d6 d5 d4 d3 d2 d1 d0 cpu control register (ccr) 0 = standard drive 1 = 33% drive on a19-a0, d7-d0 lncpuctl 0 = standard drive 1 = 33% drive on cpu control signals lnio 0 = standard drive 1 = 33% drive on group 1 i/o signals lnphi 0 = standard drive 1 = 33% drive on phi pin clock divide 0 = xtal/2 1 = xtal/1 standby/idle enable 00 = no standby 01 = idle after sleep 10 = standby after sleep 11 = standby after sleep 64-cycle exit (quick recovery) brext 0 = ignore busreq on standby/idle 1 = standby/idle exit on busreq
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-36 p r e l i m i n a r y ds971800401 bit 2 lnio. this bit controls the drive capability of certain external i/o pins of the z8s180/z8l180. when this bit is set to 1, the output drive capability of the following pins is reduced to 33percent of the original drive capability: /rtso/txs cka1 ckao txao txai tout bit 1 lncpuctl. this bit controls the drive capability of the cpu control pins. when this bit is set to 1, the output drive capability of the following pins is reduced to 33percent the original drive capability: /busack /rd /wr /m1 /mreq /iorq /rfsh /halt bit 0 lnad/data. this bit controls the drive capability of the address/data bus output drivers. if this bit is set to 1, the output drive capability of the address and data bus output is reduced to 33percent of its original drive capability.
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-37 1 iasci register description figure 32. asci block diagram internal address/data bus asci transmit data register ch 0: tdr0 asci transmit shift register* ch 0: tsr0 asci receive data fifo ch 0: rdr0 asci receive shift register* ch 0: rsr0 (8) asci control register a ch 0: cntla0 (8) asci control register b ch 0: cntb0 (8) asci status register ch 0: stat0 (8) asci extension control reg. ch 0: asext0 (7) asci time constant low ch 0: astcol (8) asci time constant high ch 0: astcoh (8) asci status fifo ch 0 asci transmit data register ch 1: tdr1 asci transmit shift register* ch 1: tsr1 asci receive data fifo ch 1: rdr1 asci receive shift register* ch 1: rsr1 (8) asci control register a ch 1: cntla1 (8) asci control register b ch 1: cntb1 (8) asci status register ch 1: stat1 (8) asci extension control reg. ch 1: asext1 (5) asci time constant low ch 1: astcil (8) asci time constant high ch 1: astcih (8) asci status fifo ch 1 txa 0 rxa 0 r ts 0 cts 0 dcd 0 txa 1 rxa 1 cts 1 asci control baud rate generator 0 baud rate generator 1 cka 0 cka 1 f note: *not program interrupt request accessible.
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-38 p r e l i m i n a r y ds971800401 the following paragraphs explain the various functions of the asci registers. asci transmit register 0. when the asci transmit register receives data from the asci transmit data reg- ister (tdr), the data is shifted out to the txa pin. when transmission is completed, the next byte (if available) is automatically loaded from tdr into tsr and the next transmission starts. if no data is available for transmission, tsr idles by outputting a continuous high level. this reg- ister is not program accessible asci transmit data register 0,1 (tdr0, 1: i/o address = 06h, 07h). data written to the asci transmit data reg- ister is transferred to the tsr as soon as tsr is empty. data can be written while tsr is shifting out the previous byte of data. thus, the asci transmitter is double buffered. data can be written into and read from the asci transmit data register. if data is read from the asci transmit data register, the asci data transmit operation will not be af- fected by this read operation asci receive shift register 0,1 (rsr0,1). this register receives data shifted in on the rxa pin. when full, data is automatically transferred to the asci receive data regis- ter (rdr) if it is empty. if rsr is not empty when the next incoming data byte is shifted in, an overrun error occurs. this register is not program accessible. asci receive data fifo 0,1 (rdr0, 1:i/o address = 08h, 09h). the asci receive data register is a read-only reg- ister. when a complete incoming data byte is assembled in rsr, it is automatically transferred to the 4 character receive data first-in first-out (fifo) memory. the oldest character in the fifo (if any) can be read from the receive data register (rdr). the next incoming data byte can be shifted into rsr while the fifo is full. thus, the asci re- ceiver is well buffered. asci status fifo this 4 entry fifo contains parity error, framing error, rx overrun, and break status bits associated with each char- acter in the receive data fifo. the status of the oldest character (if any) can be read from the asci status regis- ters as described below
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-39 1 asci channel control register a mpe: multi-processor mode enable (bit 7). the asci has a multiprocessor communication mode that utilizes an extra data bit for selective communication when a number of processors share a common serial bus. multiprocessor data format is selected when the mp bit in cntlb is set to 1. if multiprocessor mode is not selected (mp bit in cntlb = 0), mpe has no effect. if multiprocessor mode is select- ed, mpe enables or disables the ?ake-up?feature as fol- lows. if mbe is set to 1, only received bytes in which the mpb (multiprocessor bit) = 1 can affect the rdrf and er- ror flags. effectively, other bytes (with mpb = 0) are ?g- nored?by the asci. if mpe is reset to 0, all bytes, regard- less of the state of the mpb data bit, affect the redr and error flags. mpe is cleared to 0 during reset. re: receiver enable (bit 6). when re is set to 1, the asci transmitter is enabled. when te is reset to 0, the transmitter is disables and any transmit operation in progress is interrupted. however, the tdre flag is not re- set and the previous contents of tdre are held. te is cleared to 0 in iostop mode during reset. te: transmitter enable (bit 5) . when te is set to 1, the asci receiver is enabled. when te is reset to 0, the trans- mitter is disabled and any transmit operation in progress is interrupted. however, the tdre flag is not reset and the previous contents of tdre are held. te is cleared to 0 in iostop mode during reset. rts0 : request to send channel 0 (bit 4 in cntla0 only). if bit 4 of the system configuration register is 0, the rts0 /txs pin has the rts0 function. rts0 allows the asci to control (start/stop) another communication devic- es transmission (for example, by connecting to that de- vice? cts input). rts0 is essentially a 1 bit output port, having no side effects on other asci registers or flags. bit 4 in cntla1 is used. cka1d = 1, cka1/tend 0 pin = tend 0 cka1d = 0, cka1/tend 0 pin = cka1 cleared to 0 on reset. mpbr/efr: multiprocessor bit receive/error flag re- set (bit 3). when multiprocessor mode is enabled (mp in cntlb = 1), mpbr, when read, contains the value of the mpb bit for the last receive operation. when written to 0, the efr function is selected to reset all error flags (ovrn, fe, pe and brk in the asext register) to 0. mpbr/efr is undefined during reset. figure 33. asci channel control register a bit mpe re r/w r/w r/w te 76 5 4 3 21 0 r ts 0 mpbr/ mod2 mod1 mod0 r/w r/w asci control register a 0 (cntla0: i/o address = 00h) r/w r/w r/w efr bit mpe re r/w r/w r/w te 76 5 4 3 21 0 mod2 mod1 mod0 r/w r/w asci control register a 1 (cntla1: i/o address = 01h) r/w r/w r/w mpbr/ efr cka1d
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-40 p r e l i m i n a r y ds971800401 mod2, 1, 0: asci data format mode 2, 1, 0 (bits 2-0). these bits program the asci data format as follows. mod2 = 0 ? 7 bit data = 1 ? 8 bit data mod1 = 0 ? no parity = 1 ? parity enabled mod0 = 0 ? 1 stop bit = 1 ? 2 stop bits the data formats available based on all combinations of mod2, mod1, and mod0 are shown in table 5-6. asci channel control register b mpbt: multiprocessor bit transmit (bit 7). when multi- processor communication format is selected (mp bit = 1), mpbt is used to specify the mpb data bit for transmission. if mpbt = 1, then mpb = 1 is transmitted. if mpbt = 0, then mpb = 0 is transmitted. mpbt state is undefined dur- ing and after reset. mp: multiprocessor mode (bit 6). when mp is set to 1, the data format is configured for multiprocessor mode based on the mod2 (number of data bits) and mod0 (number of stop bits) bits in cntla. the format is as fol- lows. start bit + 7 or 8 data bits + mpb bit + 1 or 2 stop bits note that multiprocessor (mp=1) format has no provision for parity. if mp = 0, the data format is based on mod0, mod1, mod2, and may include parity. the mp bit is cleared to 0 during reset. cts /ps: clear to send/prescale (bit 5). when read, /cts/ps reflects the state of the external /cts input. if the /cts input pin is high, /cts/ps will be read as 1. note that when the /cts input pin is high, the tdre bit is in- hibited (i.e. held at 0). for channel 1, the /cts input is mul- tiplexed with rxs pin (clocked serial receive data). thus, /cts/ps is only valid when read if the channel 1 cts1e bit = 1 and the /cts input pin function is selected. the read data of /cts/ps is not affected by reset. if the ss2-0 bits in this register are not 111, and the brg mode bit in the asext register is 0, then writing to this bit sets the prescale (ps) control as described in the following ?lock modes?section. under those circumstances, a 0 in- dicates a divide by 10 prescale function while a 1 indicates divide by 30. the bit resets to 0. peo: parity even odd (bit 4). peo selects oven or odd parity. peo does not affect the enabling/disabling of parity (mod1 bit of cntla). if peo is cleared to 0, even parity is selected. if peo is set to 1, odd parity is selected. peo is cleared to 0 during reset. dr: divide ratio (bit 3). if the x1 bit in the asext regis- ter is 0, this bit specifies the divider used to obtain baud rate from the data sampling clock. if dr is reset to 0, di- vide- by-16 is used, while if dr is set to 1 divide-by-64 is used. dr is cleared to 0 during reset. ss2,1,0: source/speed select 2,1,0 (bits 2-0). first, if these bits are 111, as they are after a reset, the cka pin table 5. data formats mod2 mod1 mod0 data format 0 0 0 start + 7 bit data + 1 stop 0 0 1 start + 7 bit data + 2 stop 0 1 0 start + 7 bit data + parity + 1 stop 0 1 1 start + 7 bit data + parity + 2 stop 1 0 0 start + 8 bit data + 1 stop 1 0 1 start + 8 bit data + 2 stop 1 1 0 start + 8 bit data + parity + 1 stop 1 1 1 start + 8 bit data + parity + 2 stop figure 34. asci channel control register b bit mpbt mp r/w r/w r/w cts / 76 5 4 3 21 0 peo dr ss2 ss1 ss0 r/w r/w asci control register b 1 (cntlb1: i/o address = 03h) r/w r/w r/w asci control register b 0 (cntlb0: i/o address = 02h) ps
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-41 1 is used as a clock input, and is divided by 1, 16, or 64 de- pending on the dr bit and the x1 bit in the asext register. if these bits are not 111 and the brg mode bit is asext is 0, then these bits specify a power-of-two divider for the phi clock as shown in table 9. setting or leaving these bits as 111 makes sense for a channel only when its cka pin is selected for the cka function. ckao/cks has the ckao function when bit 4 of the system configuration register is 0. dcd0 /cka1 has the cka1 function when bit 0 of the interrupt edge register is 1. asci status register 0, 1 (stat0, 1) each channel status register allows interrogation of asci communication, error and modem control signal status, and enabling or disabling of asci interrupts. rdrf: receive data register full (bit 7). rdrf is set to 1 when an incoming data byte is loaded into an empty rx fifo. note that if a framing or parity error occurs, rdrf is still set and the receive data (which generated the error) is still loaded into the fifo. rdrf is cleared to 0 by reading rdr and last character in the fifo from iostop mode, during reset and for asci0 if the /dcd0 input is auto-en- abled and is negated (high). ovrn: overrun error (bit 6). an overrun condition oc- curs if the receiver has finished assembling a character but the rx fifo is full so there is no room for the character. however, this status bit is not set until the last character re- ceived before the overrun becomes the oldest byte in the fifo. this bit is cleared when software writes a 1 to the efr bit in the cntla register, and also by reset, in iostop mode, and for asci0 if the /dcd0 pin is auto en- abled and is negated (high). note that when an overrun occurs, the receiver does not place the character in the shift register into the fifo, nor any subsequent characters, until the last good character has come to the top of the fifo so that ovrn is set, and software then writes a 1 to efr to clear it. table 6. divide ratio ss2 ss1 ss0 divide ratio 000 ? 1 001 ? 2 010 ? 4 011 ? 8 100 ? 16 101 ? 32 110 ? 64 1 1 1 external clock figure 35. asci status registers bit rdrf ovrn r r r/w pe 76 5 4 3 2 1 0 fe re dcd 0 tdre tie r r asci status register 0 (stat0: i/o address = 04h) r r r/w bit rdrf ovrn r r/w pe 76 5 4 3 2 1 0 fe re tdre tie rr asci status register 1 (stat1: i/o address = 05h) r r r/w ctsie r/w
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-42 p r e l i m i n a r y ds971800401 pe: parity error (bit 5). a parity error is detected when parity checking is enabled by the mod1 bit in the cnt1la register being 1, and a character has been assembled in which the parity does not match the peo bit in the cntlb register. however, this status bit is not set until/unless the error character becomes the oldest one in the rxfifo. pe is cleared when software writes a 1 to the efr bit in the cntrla register, and also by reset, in iostop mode, and for asci0 if the /dcd0 pin is auto-enabled and is ne- gated (high). fe: framing error (bit 4). a framing error is detected when the stop bit of a character is sampled as 0/space. however, this status bit is not set until/unless the error character becomes the oldest one in the rxfifo. fe is cleared when software writes a 1 to the efr bit in the cntla register, and also by reset, in iostop mode, and for ascio if the /dcdo pin is auto-enabled and is negated (high). rei: receive interrupt enable (bit 3). rie should be set to 1 to enable asci receive interrupt requests. when rie is 1, the receiver requests an interrupt when a character is received and rdrf is set, but only if neither dma chan- nel has its request-routing field set to receive data from this asci. that is, if sm1-0 are 11 and sar17-16 are 10, or dim1 is 1 and iar17-16 are 10, then asci1 doesn't re- quest an interrupt for rdrf. if rie is 1, either asci re- quests an interrupt when ovrn, pe or fe is set, and asci0 requests an interrupt when /dcd0 goes high. rie is cleared to 0 by reset. dcd0 : data carrier detect (bit 2 stat0). this bit is set to 1 when the pin is high. it is cleared to 0 on the first read of stat0 following the pin's transition from high to low and during reset. bit 6 of the asext0 register is 0 to se- lect auto-enabling, and the pin is negated (high). channel 1 has an external cts1 input which is multiplexed with the receive data pin rsx for the csi/o. bit 2 = 0; select rxs function. bit 2 = 1; select cts1 function. tdre: transmit data register empty (bit 1). tdre = 1 indicates that the tdr is empty and the next transmit data byte is written to tdr. after the byte is written to tdr, tdre is cleared to 0 until the asci transfers the byte from tdr to the tsr and then tdre is again set to 1. tdre is set to 1 in iostop mode and during reset. on ascio, if the cts0 pin is auto-enabled in the asext0 registers and the pin is high, tdre is reset to 0. tie: transmit interrupt enable (bit 0). tie should be set to 1 to enable asci transmit interrupt requests. if tie = 1, an interrupt will be requested when tdre = 1. tie is cleared to 0 during reset. asci transmit data registers register addresses 06h and 07h hold the asci transmit data for channel 0 and channel 1, respectively. channel 0 mnemonics tdr0 address (06h) channel 1 mnemonics tdr1 address (07h) figure 36. asci register asci transmit -- -- -- -- -- -- -- 76 54 3 2 1 0 -- -- channel 0 figure 37. asci register asci transmit -- -- -- -- -- -- -- 76 54 3 2 1 0 -- -- channel 1
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-43 1 asci receive register register addresses 08h and 09h hold the asci receive data for channel 0 and channel 1, respectively. channel 0 mnemonics tsr0 -- address (08h) channel 1-- mnemonics tsr1 address (09h) csi/o control/status register (cntr: i/o address = 0ah). cntr is used to monitor csi/o status, enable and disable the csi/o, enable and disable interrupt generation, and select the data clock speed and source. ef: end flag (bit 7). ef is set to 1 by the csi/o to indicate completion of an 8-bit data transmit or receive operation. if eie (end interrupt enable) bit = 1 when ef is set to 1, a cpu interrupt request is generated. program access of trdr only occurs if ef = 1. the csi/o clears ef to 0 when trdr is read or written. ef is cleared to 0 during reset and iostop mode. eie: end interrupt enable (bit 6). eie is set to 1 to gen- erate a cpu interrupt request. the interrupt request is in- hibited if eie is reset to 0. eie is cleared to 0 during re- set. re: receive enable (bit 5). a csi/o receive operation is started by setting re to 1. when re is set to 1, the data clock is enabled. in internal clock mode, the data clock is output from the cks pin. in external clock mode, the clock is input on the cks pin. in either case, data is shifted in on the rxs pin in synchronization with the (internal or exter- nal) data clock. after receiving 8 bits of data, the csi/o au- tomatically clears re to 0, ef is set to 1, and an interrupt (if enabled by eie = 1) is generated. re and te are never both set to 1 at the same time. re is cleared to 0 during reset and istop mode. figure 38. asci receive register channel 0 asci transmit data -- -- -- -- -- -- -- 76 54 3 2 1 0 -- -- figure 39. asci receive register channel 1r asci transmit data -- -- -- -- -- -- -- 76 54 3 2 1 0 -- -- figure 40. csi/o control register bit ef eie r/w r/w r/w re 76 5 4 3 21 0 te __ ss2 ss1 ss0 r r/w r/w r/w
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-44 p r e l i m i n a r y ds971800401 transmit enable (bit 4). a csi/o transmit operation is started by setting te to 1. when te is set to 1, the data clock is enabled. when in internal clock mode, the data clock is output from the cks pin. in external clock mode, the clock is input on the cks pin. in either case, data is shifted out on the txs pin synchronous with the (internal or external) data clock. after transmitting 8 bits of data, the csi/o automatically clears te to 0, ef is set to 1, and an interrupt (if enabled by eie = 1) is generated. te and re are never both set to 1 at the same time. te is cleared to 0 during reset and iostop mode. ss2, 1, 0: speed select 2, 1, 0 (bits 2-0). ss2, ss1 and ss0 select the csi/o transmit/receive clock source and speed. ss2, ss1 and ss0 are all set to 1 during reset. table 10 shows csi/o baud rate selection. after reset, the cks pin is configured as an external clock input (ss2, ss1, ss0 = 1). changing these values causes cks to become an output pin and the selected clock is output when transmit or receive operations are en- abled. csi/o transmit/receive data register (trdr: i/o address = 0bh). timer data register channel 0l tmdr0l 0ch timer data register channel 0h tmdr0h 0d h table 7. csi/o baud rate selection ss2 ss1 ss0 divide ratio 000 ? 20 001 ? 40 010 ? 80 011 ? 160 100 ? 320 101 ? 640 110 ? 1280 1 1 1 external clock input (less than ? 20.) figure 41. csi/o transmit/receive data register 1r csi/o t/r data -- -- -- -- -- -- -- -- 76 54 32 1 -- 0 figure 42. timer register channel ol figure 43. timer data register channel oh asci receive data -- -- -- -- -- -- -- -- 76 54 32 1 -- 0 timer data -- -- -- -- -- -- -- -- 76 54 32 1 -- 0
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-45 1 timer reload register 0l rldr0l 0e h timer reload register 0h rldr0h 0f h timer control register (tcr) tcr monitors both channels (prt0, prt1) tmdr status. it also controls enabling and disabling of down counting and interrupts along with controlling output pin a18/tout for prt1. tif1: timer interrupt flag 1 (bit 7). when tmdr1 decre- ments to 0, tif1 is set to 1. this generates an interrupt re- quest if enabled by tie1 = 1. tif1 is reset to 0 when tcr is read and the higher or lower byte of tmdr1 is read. dur- ing reset, tif1 is cleared to 0. tif0: timer interrupt flag 0 (bit 6). when tmdr0 decre- ments to 0, tif0 is set to 1. this generates an interrupt re- quest if enabled by tie0 = 1. tif0 is reset to 0 when tcr is read and the higher or lower byte of tmdr0 is read. dur- ing reset, tif0 is cleared to 0. tie1: timer interrupt enable 1 (bit 5). when tie0 is set to 1, tif1 = 1 generates a cpu interrupt request. when tie0 is reset to 0, the interrupt request is inhibited. during reset, tie0 is cleared to 0. toc1, 0: timer output control (bits 3, 2). toc1 and toc0 control the output of prt1 using the multiplexed tout/dreq pin as shown in table 11. during reset, toc1 and toc0 are cleared to 0. if bit 3 of the iar1b reg- ister is 1, the tout function is selected. by programming toc1 and toc0, the tout/dreq pin can be forced high, low, or toggled when tmdr1 decrements to 0. figure 44. timer reload register low timer reload data -- -- -- -- -- -- -- -- 76 54 32 1 -- 0 figure 45. timer reload register channel timer reload data -- -- -- -- -- -- -- -- 76 54 32 1 -- 0 figure 46. timer control register (tcr: i/o address = 10h) bit tif1 tif0 r/w r/w r/w tie1 76 5 4 3 21 0 tie0 toc0 tde1 tde0 r r r/w r/w r/w toc1 table 8. timer output control toc1 toc0 output 0 0 inhibited the tout/dreq pin is not affected by the prt. 0 1 toggled if bit 3 of iar1b is 1, the tout/dreq pin is toggles or set low or high as indicated. 10 0 11 1
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-46 p r e l i m i n a r y ds971800401 tde1, 0: timer down count enable (bits 1, 0). tde1 and tde0 enable and disable down counting for tmdr1 and tmdr0, respectively. when tden (n = 0, 1) is set to 1, down counting is stopped and tmdrn is freely read or written. tde1 and tde0 are cleared to 0 during reset and tmdrn will not decrement until tden is set to 1. asci extension control register channel 0 (asext0) and channel 1 (asext1) note: this register controls functions that have been added to the ascis in the z80180/z8s180/z8l180 family. note: all bits in this register reset to zero. dcd0 dis (bit 6, asci0 only). if this bit is 0, then the dcd0 pin ?uto-enables?the asci0 receiver, such that when the pin is negated/high, the receiver is held in a re- set state. the state of the dcd -pin has no effect on re- ceiver operation. in either state of this bit, software can read the state of the dcd0 pin in the stat0 register, and the receiver will interrupt on a rising edge of dcd0 . cts0 dis (bit 5, asci0 only). if this bit is 0, then the cts0 pin ?uto-enables?the ascio transmitter, in that when the pin is negated/high, the tdre bit in the stat0 register is forced to 0. if this bit is 1, the state of the cts0 pin has no effect on the transmitter. regardless of the state of this bit, software can read the state of the cts0 pin the cntlb0 register. x1 (bit 4). if this bit is 1, the clock from the baud rate gen- erator or cka pin is taken as a ?x?bit clock (this is some- times called ?sochronous?mode). in this mode, receive data on the rxa pin must be synchronized to the clock on the cka pin, regardless of whether cka is an input or an output. if this bit is 0, the clock from the baud rate gener- ator or cka pin is divided by 16 or 64 per the dr bit in cntlb register, to obtain the actual bit rate. in this mode, receive data on the rxa pin need not be synchronized to a clock. brg mode (bit 3). if the ss2-0 bits in the cntlb register are not 111, and this bit is 0, this asci's baud rate gen- erator divides phi by 10 or 30, depending on the dr bit in cntlb, and then by a power of two selected by the ss2- 0 bits, to obtain the clock that is presented to the transmit- ter and receiver and that can be output on the cka pin. if ss2-0 are not 111, and this bit is 1, the baud rate gener- ator divides phi by twice (the 16-bit value programmed into the time constant registers, plus two). this mode is identical to the operation of the baud rate generator in the escc. break enable (bit 2). if this bit is 1, the receiver will detect break conditions and report them in bit 1, and the transmit- ter will send breaks under the control of bit 0. break detect (bit 1). the receiver sets this read-only bit to 1 when an all-zero character with a framing error be- comes the oldest character in the rx fifo. the bit is cleared when software writes a 0 to the efr bit in cntla register, also by reset, by iostop mode, and for ascio if the dcd0 pin is auto-enabled and is negated (high). send break (bit 0). if this bit and bit 2 are both 1, the trans- mitter holds the txa pin low to send a bread condition. the duration of the bread is under software control (one of the prts or ctcs can be used to time it). this bit resets to 0, in which state txa carries the serial output of the transmitter. figure 47. asci extension control registers, channel 0 and 1 bit dcdo 76 5 4 3 21 0 xi brgo break break send asci extension control register 0(asext0 i/o address = 12h) ctso mode nab break bit 76 5 4 3 21 0 xi brgi break break send mode enab break asci extension control register 1 (asext1 i/o address = 13h) reserved reserved reserved reserved
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-47 1 timer data register channel 1l mnemonic tmdr1l address 14 timer data register channel 1h mnemonic tmdr1h address 15 timer reload register channel 1l mnemonic rldr1l address 16 timer reload register channel 1l mnemonic rldr1h address 17 free running counter (read only) mnemonic frc address 18 figure 48. timer data register 1l figure 49. timer data register 1h figure 50. timer reload channel 1l 76 54 32 1 0 timer data 76 54 32 1 0 timer data 76 54 32 1 0 reload data figure 51. timer relaod register channel 1l figure 52. free running counter 76 54 32 1 0 reload data 76 54 32 1 0 counting data
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-48 p r e l i m i n a r y ds971800401 asci time constant registers if the ss2-0 bits of the cntla register are not 111, and the brg mode bit in the asext register is 1, the asci divides the phi clock by twice (the 16-bit value in these registers, plus two), to obtain the clock that is presented to the trans- mitter and receiver for division by 1, 16, or 64 and that can be output on the cka1 pin. figure 53. asci time constant registers bit 76 5 4 3 21 0 bit 76 5 4 3 21 0 asci time constant register 0 low (astcol, i/o address iah) asci time constant register 1 low (astcil), i/o address ich) asci time constant register 0 high (astcoh, i/o address ibh) asci time constant register 1 high (astcih), i/o address idh) ls 8 bits of time constant ms 8 bits of time constant
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-49 1 clock multiplier register (z180 mpu address 1eh) bit 7. x2 clock multiplier mode. when this bit is set to 1, this allows the programmer to double the internal clock from that of the external clock. this feature will only oper- ated effectively with frequencies of 10-16 mhz (20-32mhz internal). when this bit is set to 0, the z80180/z8s180/z8l180 device will operate in normal mode. upon powerup, this feature is disabled. bit 6. low noise crystal option. setting this bit to 1 will enable the low noise option for the extal and xtal pins. this option reduces the gain, in addition to reduction the output drive capability to 30% of its original drive capability. the low noise crystal option is recommended in the use of crystals for pcmcia applications where the crystal may be driven too hard by the oscillator. setting this bit to 0 will select for normal operation of the extal and xtal pins. the default for this bit is 0. note: operating restrictions for device operation are listed below. if low noise option is required, and normal device operation is needed, use the clock multiplier feature. figure 54. clock multiplier register 111 00 1 76 54 32 1 1 0 1 reserved low noise crystal x2 clock multiplier table 9. low noise option low noise addr 1e, bit 6=1 normal addr 1e, bit 6=0 20 mhz @ 4.5v, 100 c 33 mhz @ 4.5v, 100 c 10 mhz @ 3.0v, 100 c 20 mhz @ 3.0v, 100 c
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-50 p r e l i m i n a r y ds971800401 dma source address register channel 0 (sar0: i/o address = 20h to 22h) specifies the physical source address for channel 0 transfers. the register contains 20 bits and can specify up to 1024 kb memory addresses or up to 64 kb i/o addresses. channel 0 source can be mem- ory, i/o, or memory mapped i/o. for i/o, the ms bits of this register identify the request handshake signal. dma source address register, channel 0l mnemonic sar0l address 20 dma source address register, channel 0h mnemonic sar0h address 21 dma source address register channel 0b mnemonics sar0b address 22 figure 55. dma source address register 0l figure 56. dma source address register 0h dma channel 0 address -- -- -- -- -- -- -- -- 76 54 32 1 -- 0 dma channel 0 address -- -- -- -- -- -- -- 76 54 32 1 -- 0 figure 57. dma source address register 0b dma channel b address -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 76 54 32 1 -- 0
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-51 1 dma destination address register channel 0 (dar0: i/o address = 23h to 25h) specifies the physical destination address for channel 0 transfers. the register con- tains 20 bits and can specify up to 1024 kb memory addresses or up to 64 kb i/o addresses. channel 0 destination can be memory, i/o, or memory mapped i/o. for i/o, the ms bits of this register identify the request handshake signal for channel 0. dma destination address register channel 0l mnemonic dar0l address 23 dma destination address register channel 0h mnemonic dar0h address 24 dma destination address register channel 0b mnemonic dar0b address 25 note: in the r1 and z mask, these dma registers are expanded from 4 bit to 3 bits in the package version of cp- 68 figure 58. dma destination address register channel 0l figure 59. dma destination address register channel 0h figure 60. dma destination address register channel 0b a19* a18 a17 a16 dma transfer request x x 0 0 dreq0 x x 0 1 tdr0 (asci0) x x 1 0 tdr1 (asci1) x x 1 1 not used
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-52 p r e l i m i n a r y ds971800401 dma byte count register channel 0 (bcro: i/o address = 26h to 27h) specifies the number of bytes to be transferred. this register contains 16 bits and may specify up to 64 kb transfers. when one byte is transferred, the register is decremented by one. if ??bytes should be transferred, ??must be stored before the dma operation. note: all dma count register channels are undefined during reset. dma byte count register channel 0l mnemonic bcr0l address 26 dma byte count register channel 0h mnemonic bcr0h address 27 dma byte count register channel 1l mnemonic bcr1l address 2e dma byte count register channel 0h mnemonic bcr1h address 2f figure 61. dma byte count register 0l figure 62. dma byte count register 0h figure 63. dma byte count register 1l figure 64. dma byte count register 0h
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-53 1 dma memory address register channel 1 (mar1: i/o address = 28h to 2ah) specifies the physical memory address for channel 1 transfers. this may be destina- tion or source memory address. the register contains 20 bits and may specify up to 1024 kb memory address. dma memory address register, channel 1l mnemonic mar1l address 28 dma memory address register, channel 1h. mnemonic mar1h address 29 dma memory address register, channel 1b mnemonic mar1b address 2a figure 65. dma memory address register, channel 1l figure 66. dma memory address register, channel 1h figure 67. dma memory address register, channel 1b
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-54 p r e l i m i n a r y ds971800401 dma i/o address register channel 1 (iar1: i/o address = 2bh to 2dh) specifies the i/o ad- dress for channel 1 transfers. this may be destination or source i/o address. the register contains 16 bits of i/o ad- dress; its most significant byte identifies the request handshake signal and controls the alternating channel feature. all bits in iar1b reset to 0. dma i/o address register channel 1l mnemonic iar1l address 2b dma i/o address register channel 1h mnemonic iar1h address 2c dma i/o address register channel 1b mnemonic iar1b address 2d figure 68. iar ms byte register (iarib: i/o address 2dh) bit a/t a/t 76 54 3 2 1 0 f c tout /dreq req 1 sel figure 69. dma i/o address register channel 1l figure 70. dma i/o address register channel 1h figure 71. dma i/o address register channel 1b
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-55 1 dma status register (dstat) dstat is used to enable and disable dma transfer and dma termination interrupts. dstat also indicates dma transfer status, in other words, completed or in progress. mnemonic dstat address 30 de1: dma enable channel 1 (bit 7). when de1 = 1 and dme = 1, channel 1 dma is enabled. when a dma trans- fer terminates (bcr1 = 0), de1 is reset to 0 by the dmac. when de1 = 0 and the dma interrupt is enabled (die1 = 1), a dma interrupt request is made to the cpu. to perform a software write to de1, dwe1 should be writ- ten with 0 during the same register write access. writing de1 to 0 disables channel 1 dma, but dma is restartable. writing de1 to 1 enables channel 1 dma and automatical- ly sets dme (dma main enable) to 1. de1 is cleared to 0 during reset. de0: dma enable channel 0 (bit 6). when de0 = 1 and dme = 1, channel 0 dma is enabled. when a dma trans- fer terminates (bcr0 = 0), de0 is reset to 0 by the dmac. when de0 = 0 and the dma interrupt is enabled (die0 = 1), a dma interrupt request is made to the cpu. to perform a software write to de0, dwe0 should be writ- ten with 0 during the same register write access. writing de0 to 0 disables channel 0 dma. writing de0 to 1 en- ables channel 0 dma and automatically sets dme (dma main enable) to 1. de0 is cleared to 0 during reset. dwe1 : de1 bit write enable (bit 5). when performing any software write to de1, dwe1 should be written with 0 during the same access. dwe1 always reads as 1. dwe0 : de0 bit write enable (bit 4). when performing any software write to de0, dwe0 should be written with 0 during the same access. dwe0 always reads as 1. die1: dma interrupt enable channel 1 (bit 3). when die0 is set to 1, the termination channel 1 dma transfer (indicated when de1 = 0) causes a cpu interrupt request to be generated. when die0 = 0, the channel 0 dma ter- mination interrupt is disabled. die0 is cleared to 0 during reset. die0: dma interrupt enable channel 0 (bit 2). when die0 is set to 1, the termination channel 0 of dma transfer (indicated when de0=0) causes a cpu interrupt request to be generated. when die0=0, the channel 0 dma termina- tion interrupt is disabled. die0 is cleared to 0 during re- set. dme: dma main enable (bit 0). a dma operation is only enabled when its de bit (de0 for channel 0, de1 for chan- nel 1) and the dme bit is set to 1. when nmi occurs, dme is reset to 0, thus disabling dma activity during the nmi interrupt service routine. to restart dma, de- and/or de1 should be written with 1 (even if the contents are already 1). this automatically sets dme to 1, allowing dma operations to continue. note that dme can- not be directly written. it is cleared to 0 by nmi or indirectly set to 1 by setting de0 and/or de1 to 1. dme is cleared to 0 during reset. figure 72. dma status register (dstat: i/o address = 30h) bit de1 de0 d we1 76 5 4 3 2 1 0 r/w r/w w d we0 die1 die0 dme w r/w r/w r
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-56 p r e l i m i n a r y ds971800401 dma mode register (dmode). dmode is used to set the addressing and transfer mode for channel 0. mnemonic dmode address 31h dm1, dm0: destination mode channel 0 (bits 5,4) spec- ifies whether the destination for channel 0 transfers is memory or i/o, and whether the address should be incre- mented or decremented for each byte transferred. dm1 and dm0 are cleared to 0 during reset. sm1, sm0: source mode channel 0 (bits 3, 2) specifies whether the source for channel 0 transfers is memory or i/o, and whether the address should be incremented or decremented for each byte transferred. figure 73. dma mode register (dmode: i/o address = 31h) bit dm1 dm0 76 5 4 3 2 1 0 r/w r/w sm1 sm0 mmod r/w r/w r/w table 10. channel 0 destination memory dm1 dm0 memory i/o increment/decrement 0 0 memory +1 0 1 memory 1 1 0 memory xed 1 1 i/o ?ed table 11. channel 0 source memory sm1 sm0 memory i/o increment/decrement 0 0 memory +1 0 1 memory 1 1 0 memory xed 1 1 i/o ?ed
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-57 1 table 12 shows all dma transfer mode combinations of dm0, dm1, sm0, and sm1. since i/o to/from i/o transfers are not implemented, 12 combinations are available. mmod: memory mode channel 0 (bit). when channel 0 is configured for memory to/from memory transfers there is no request handshake signal to control the transfer tim- ing. instead, two automatic transfer timing modes are se- lectable: burst (mmod = 1) and cycle steal (mmod = 0). for burst memory to/from memory transfers, the dmac takes control of the bus continuously until the dma transfer completes (as shown by the byte count register = 0). in cy- cle steal mode, the cpu is given a cycle for each dma byte transfer cycle until the transfer is completed. for channel 0 dma with i/o source or destination, the se- lected request signal times the transfer and thus mmod is ignored. mmod is cleared to 0 during reset. table 12. transfer mode combinations address dm1 dm0 sm1 sm0 transfer mode increment/decrement 0000 memory ? memory sar0+1, dar0+1 0001 memory ? memory sar0?, dar0+1 0010 memory* ? memory sar0 ?ed, dar0+1 0011 i/o ? memory sar0 ?ed, dar0+1 0100 memory ? memory sar0+1, dar0? 0101 memory ? memory sar0?, dar0? 0110 memory* ? memory sar0 ?ed, dar0? 0111 i/o ? memory sar0 ?ed, dar0? 1000 memory ? memory* sar0+1, dar0 ?ed 1001 memory ? memory* sar0?, dar0 ?ed 1010 reserved 1011 reserved 1100 memory ? i/o sar0+1, dar0 ?ed 1101 memory i/o sar0?, dar0 ?ed 1110 reserved 1110 reserved note: * includes memory mapped i/o.
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-58 p r e l i m i n a r y ds971800401 dma/wait control register (dcntl) dcntl controls the insertion of wait states into dmac (and cpu) accesses of memory or i/o. also, it defines the request signal for each channel as level or edge sense. dcntl also sets the dma transfer mode for channel 1, which is limited to memory to/from i/o transfers. mwi1, mwi0: memory wait insertion (bits 7-6). speci- fies the number of wait states introduced into cpu or dmac memory access cycles. mwi1 and mwi0 are set to 1 during reset. i wi1, iwi0: i/o wait insertion (bits 5-4). specifies the number of wait states introduced into cpu or dmac i/o access cycles. iwi1 and iwi0 are set to 1 during reset. see the section on wait-state generation for details. dms1, dms0: dma request sense (bits 3-2). dms1 and dms0 specify the dma request sense for channel 0 and channel 1 respectively. when reset to 0, the input is level sense. when set to 1, the input is edge sense. dms1 and dms0 are cleared to 0 during reset. typically, for an input/source device, the associated dms bit should be programmed as 0 for level sense because the device has a relatively long time to update its request signal after the dma channel reads data from it in the first of the two machine cycles involved in transferring a byte. an output/destination device has much less time to update its request signal, after the dma channel starts a write op- eration to it, as the second machine cycle of the two cycles involved in transferring a byte. with zero-wait state i/o cy- cles, which apply only to the ascis, it is impossible for a device to update its request signal in time, and edge sens- ing must be used. figure 74. dma/wait control register (dcntl: i/o address = 32h) bit mwi1 iwi0 76 54 3 2 1 0 r/w r/w dms1 dms0 dim1 r/w r/w r/w mwi0 iwi1 dim0 r/w r/w r/w mwi1 mwi0 wait state 000 011 102 113 iwi1 iwi0 wait state 000 012 103 114 dmsi sense 1 edge sense 0 level sense
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-59 1 with one-wait-state i/o cycles (the fastest possible except for the ascis), it is unlikely that an output device will be able to update its request in time, and edge sense is re- quired. dim1, dim0: dma channel 1 i/o and memory mode (bits 1-0). specifies the source/destination and address modifier for channel 1 memory to/from i/o transfer modes. dim1 and dim0 are cleared to 0 during reset. interrupt vector low register mnemonic: il address 33 bits 7-5 of il are used as bits 7-5 of the synthesized inter- rupt vector during interrupts for the int1 and int2 pins and for the dmas, ascis, prts, and csi/o. these three bits are cleared to 0 during reset (figure 75). int/trap control register mnemonics itc address 34 int/trap control register (itc, i/o address 34h). this register is used in handling trap interrupts and to enable or disable maskable interrupt level 0 and the int1 and int2 pins. trap (bit 7). this bit is set to 1 when an undefined op- code is fetched. trap can be reset under program control by writing it with a 0, however, it cannot be written with 1 under program control. trap is reset to 0 during reset. ufo: undefined fetch object (bit 6). when a trap in- terrupt occurs, the contents of ufo allow determination of the starting address of the undefined instruction. this is necessary since the trap may occur on either the second or third byte of the opcode. ufo allows the stacked pc value to be correctly adjusted. if ufo = 0, the first opcode should be interpreted as the stacked pc-1. if ufo = 1, the first opcode address is stacked pc-2. ufo is read-only. ite2, 1, 0: interrupt enable 2, 1, 0 (bits 2-0). ite2 and ite1 enable and disable the external interrupt inputs /int2 and /int1, respectively. ite0 enables and disables inter- rupts from the on-chip escc, ctcs and bidirectional cen- tronics controller as well as the external interrupt input /int0. a 1 in a bit enables the corresponding interrupt level while a 0 disables it. a reset sets ite0 to 1 and clears ite1 and ite2 to 0. trap interrupt. the z80180/z8s180/z8l180 generates a non-maskable (not affected by the state of ief1) trap interrupt when an undefined opcode fetch occurs. this feature can be used to increase software reliability, imple- ment an ?xtended?instruction set, or both. trap may oc- cur during opcode fetch cycles and also if an undefined table 13. channel 1 transfer mode address dim1 dmi0 transfer mode increment/decrement 0 0 memory ? i/o mar1 +1, iar1 ?ed 0 1 memory ? i/o mar1?, iar1 ?ed 1 0 i/o ? memory iar1 ?ed, mar1 + 1 1 1 i/o ? memory iar1 ?ed, mar1 ? figure 75. interrupt vector low register (il: i/o address = 33h) bit il 7 il 6 interrupt source dependent code il 5 76 5 4 3 2 1 0 r/w r/w r/w programmable bit trap ufo r/w r/w r/w 76 5 4 3 2 1 0 ite2 ite1 ite0 r/w r
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-60 p r e l i m i n a r y ds971800401 opcode is fetched during the interrupt acknowledge cycle for int 0 when mode 0 is used. when a trap interrupt occurs, the z80180/z8s180/z8l180 operates as follows: 1. the trap bit in the interrupt trap/control (itc) register is set to 1. 2. the current pc (program counter) value, reflecting the location of the undefined opcode, is saved on the stack. 3. the z80180/z8s180/z8l180 vectors to logical address 0. note that if logical address 0000h is mapped to physical address 00000h, the vector is the same as for reset. in this case, testing the trap bit in itc will reveal whether the restart at physical address 00000h was caused by reset or trap. all trap interrupts occur after fetching an undefined sec- ond opcode byte following one of the ?refix?opcodes cbh, ddh, edh, or fdh, or after fetching an undefined third opcode byte following one of the ?ouble prefix?op- codes ddcbh or fdcbh. the state of the undefined fetch object (ufo) bit in itc allows trap software to correctly ?djust?the stacked pc, depending on whether the second or third byte of the op- code generated the trap. if ufo=0, the starting address of the invalid instruction is equal to the stacked pc-1. if ufo=1, the starting address of the invalid instruction is equal to the stacked pc-2. figure 76. trap timing-2 nd opcode unde?ed t 1 t 2 t 3 t tp t i t i t i t i t i t 1 t 2 t 3 t 2 t 3 t 1 t 1 t 2 a 0 -a 18 (a 19 ) f d 0 -d 7 pc 0000h sp-1 undefined mreq m1 rd wr t 3 sp-2 opcode pc h pc l 2nd opcode fetch cycle pc stacking opcode fetch cycle restart from 0000h
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-61 1 refresh control register mnemonic rcr address 36 the rcr specifies the interval and length of refresh cy- cles, while enabling or disabling the refresh function. refe: refresh enable (bit 7). refe = disables the re- fresh controller while refe = 1 enables refresh cycle in- sertion. refe is set to 1 during reset. refw: refresh wait (bit 6). refw = 0 causes the re- fresh cycle to be two clocks in duration. refw = 1 causes the refresh cycle to be three clocks in duration by adding a refresh wait cycle (trw). refw is set to 1 during reset. cyc1, 0: cycle interval (bit 1,0). cyc1 and cyc0 spec- ify the interval (in clock cycles) between refresh cycles. in the case of dynamic rams requiring 128 refresh cycles ev- ery 2 ms (0r 256 cycles in every 4 ms), the required refresh interval is less than or equal to 15.625 m s. thus, the under- lined values indicate the best refresh interval depending on cpu clock frequency. cyc0 and cyc1 are cleared to 0 during reset (see table 14). figure 77. trap timing-3 rd opcode unde?ed t 1 t 2 t 3 t 1 t 2 t tp t 3 t i t i t 1 t 2 t 3 t 2 t 3 t 1 t 1 t 2 a 0 -a 18 (a 19 ) f d 0 -d 7 pc 0000h sp-1 undefined mreq m1 rd wr t 3 sp-2 opcode pc-1 h pc-1 l 3nd opcode fetch cycle pc stacking opcode fetch cycle restart memory ix + d, iy + d t i t i read cycle from 0000h figure 78. refresh control register (rca: i/o address = 36h) reserved -- -- -- -- -- -- -- 76 54 32 1 cyc1 cyc0 refw refe - -- 0
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-62 p r e l i m i n a r y ds971800401 refresh control and reset. after reset, based on the initialized value of rcr, refresh cycles will occur with an interval of 10 clock cycles and be 3 clock cycles in dura- tion. dynamic ram refresh operation 1. refresh cycle insertion is stopped when the cpu is in the following states: a. during reset b. when the bus is released in response to busreq. c. during sleep mode. d. during wait states. 2. refresh cycles are suppressed when the bus is released in response to busreq . however, the refresh timer continues to operate. thus, the time at which the first refresh cycle occurs after the z80180/z8s180/z8l180 re-acquires the bus depends on the refresh timer and has no timing relationship with the bus exchange. 3. refresh cycles are suppressed during sleep mode. if a refresh cycle is requested during sleep mode, the refresh cycle request is internally ?atched?(until replaced with the next refresh request). the ?atched refresh cycle is inserted at the end of the first machine cycle after sleep mode is exited. after this initial cycle, the time at which the next refresh cycle occurs depends on the refresh time and has no relationship with the exit from sleep mode. 4. the refresh address is incremented by one for each successful refresh cycle, not for each refresh. thus, independent of the number of ?issed?refresh requests, each refresh bus cycle will use a refresh address incremented by one from that of the previous refresh bus cycles. mmu common base register mnemonic cbr address 38 mmu common base register (cbr). cbr specifies the base address (on 4 kb boundaries) used to generate a 20- bit physical address for common area 1 accesses. all bits of cbr are reset to 0 during reset. table 14. dram refresh intervals insertion time interval cyc1 cyc0 interval : 10 mhz 8 mhz 6 mhz 4 mhz 2.5 mhz 0 0 10 states (1.0 m s)* (1.25 m s)* 1.66 m s 2.5 m s 4.0 m s 0 1 20 states (2.0 m s)* (2.5 m s)* 3.3 m s 5.0 m s 8.0 m s 1 0 40 states (4.0 m s)* (5.0 m s)* 6.6 m s 10.0 m s 16.0 m s 1 1 80 states (8.0 m s)* (10.0 m s)* 13.3 m s 20.0 m s 32.0 m s note: *calculated interval figure 79. mmu common base register (bbr: i/o address = 38h) bit cb7 cb6 r/w cb5 76 5 4 3 21 0 cb4 cb2 cb1 cb0 r/w cb3 r/w r/w r/w r/w r/w r/w
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-63 1 mmu bank base register (bbr). mnemonic bbr address 39 bbr specifies the base address (on 4 kb boundaries) used to generate a 19-bit physical address for bank area accesses. all bits of bbr are reset to 0 during reset. mmu common/bank area register (cbar). mnemonic cbar address 3a cbar specifies boundaries within the z80180/z8s180/z8l180 64 kb logical address space for up to three areas; common area), bank area and com- mon area 1. ca3-ca0:ca (bits 7-4). ca specifies the start (low) ad- dress (on 4 kb boundaries) for the common area 1. this also determines the last address of the bank area. all bits of ca are set to 1 during reset. ba-ba0 (bits 3-0). ba specifies the start (low) address (on 4 kb boundaries) for the bank area. this also deter- mines the last address of the common area 0. all bits of ba are set to 1 during reset. figure 80. mmu bank base register (bbr: i/o address = 39h) bit bb7 bb6 r/w bb5 76 5 4 3 21 0 bb4 bb2 bb1 bb0 r/w bb3 r/w r/w r/w r/w r/w r/w figure 81. mmu common/bank area register (cbar: i/o address = 3 ah bit ca3 ca2 r/w ca1 76 5 4 3 21 0 ca0 ba2 ba1 ba0 mmu common/bank area register (cbar: i/o address = 3 ah) r/w ba3 r/w r/w r/w r/w r/w r/w
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-64 p r e l i m i n a r y ds971800401 operation mode control register mnemonic omcr address 3e the z80180/z8s180/z8l180 is descended from two dif- ferent ?ncestor?processors, zilog's original z80 and the hitachi 64180. the operating mode control register (om- cr) can be programmed to select between certain differ- ences between the z80 and the 64180. m1e (m1 enable). this bit controls the m1 output and is set to a 1 during reset. when m1e=1, the m1 output is asserted low during the opcode fetch cycle, the int0 acknowledge cycle, and the first machine cycle of the nmi acknowledge. on the z80180/z8s180/z8l180, this choice makes the processor fetch an reti instruction once, and when fetch- ing an reti from zero-wait-state memory will use three clock machine cycles which are not fully z80-timing com- patible but are compatible with the on-chip ctcs. when mie=0, the processor does not drive m1 low during instruction fetch cycles, and after fetching an reti instruc- tion once with normal timing, it goes back and re-fetches the instruction using fully z80-compatible cycles that in- clude driving m1 low. this may be needed by some exter- nal z80 peripherals to properly decode the reti instruc- tion.i/o control register (icr). icr allows relocating of the internal i/o addresses. icr also controls enabling/disabling of the iostop mode (figure 84). figure 82. operating control register (omcr: i/o address = 3eh) d7 reserved d6 d5 -- ioc (r/w) m1te (w) m1e (r/w) -- -- -- -- figure 83. reti instruction sequence with mie=0 figure 84. i/o control register (icr: i/o address = 3fh) t 1 t 2 t 3 t 1 t 2 t 3 t i t i t i t 1 t 2 t 3 t 1 t 2 t 3 t i t i a 0 -a 18 (a 19 ) f d 0 -d 7 pc pc+1 pc pc+1 edh 4dh edh 4dh mreq m1 rd st ioa7 ioa6 -- -- -- -- iostp bit 7 6543210 -- r/w r/w r/w
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-65 1 ioa7, 6: i/o address relocation (bits 7,6). ioa7 and ioa6 relocate internal i/o as shown in figure 85. note that the high-order 8 bits of 16-bit internal i/o address are al- ways 0. ioa7 and ioa6 are cleared to 0 during reset. iostp. iostop mode (bit 5). iostop mode is enabled when iostp is set to 1. normal i/o operation resumes when iostop is reprogrammed or reset to 0 figure 85. i/o address relocation ioa7-ioa6 = 1 1 ioa7-ioa6 = 1 0 ioa7- ioa6 = 0 1 ioa7-ioa6 = 0 0 00ffh 00coh 00bfh 008oh 007oh 004oh 003fh 000oh
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-66 p r e l i m i n a r y ds971800401 package information figure 86. 80-pin qfp package diagram
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-67 1 figure 87. 64-pin dip package diagram figure 88. 68-pin plcc package diagram
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-68 p r e l i m i n a r y ds971800401 ordering information z80180 6, 8, 10mhz z8s180 20, 33mhz z8l180 20mhz please check availability before placing order. codes package f = plastic quad flatpack p = plastic dual in line v = plastic leaded chip carrier temperature s = 0 c to +70 c e = -40c to +85c speeds 06 = 6 mhz 08 = 8 mhz 10 = 10 mhz 20 = 20 mhz 33 = 33 mhz environmental c = plastic standard example: z 80180 08 p s c is a z80180, 08 mhz, plastic dip, 0 to +70 c, standard flow environmental flow temperature package speed product number zilog pre?
z80180/z8s180/z8l180 zilog enhanced z180 microprocessor ds971800401 p r e l i m i n a r y 1-69 1 ?1997 by zilog, inc. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of zilog, inc. the information in this document is subject to change without notice. devices sold by zilog, inc. are covered by warranty and patent indemnification provisions appearing in zilog, inc. terms and conditions of sale only. zilog, inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. zilog, inc. makes no warranty of merchantability or fitness for any purpose. zilog, inc. shall not be responsible for any errors that may appear in this document. zilog, inc. makes no commitment to update or keep current the information contained in this document. zilog? products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and zilog prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. zilog, inc. 210 east hacienda ave. campbell, ca 95008-6600 telephone (408) 370-8000 fax 408 370-8056 internet: http://www.zilog.com
z80180/z8s180/z8l180 enhanced z180 microprocessor zilog 1-70 p r e l i m i n a r y ds971800401

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